1 | # |
---|
2 | # Quirks in the DY-4 DMV177 |
---|
3 | # |
---|
4 | # $Id$ |
---|
5 | # |
---|
6 | |
---|
7 | JTAG and Caching |
---|
8 | ================ |
---|
9 | If data or code caching is enabled on certain revisions of the PPC603e, |
---|
10 | then the JTAG emulator interface become disfunctional. You can not |
---|
11 | debug using the emulator on these chip revisions. On certain revisions, |
---|
12 | it is so bad that when code caching is enabled, you can not even |
---|
13 | download code reliably to the board. |
---|
14 | |
---|
15 | Caching and Peripherals |
---|
16 | ======================= |
---|
17 | When caching is enabled, care must be exercised to insure that all |
---|
18 | peripheral addresses are still uncached. |
---|
19 | |
---|
20 | Exar 88681 Clock |
---|
21 | ================ |
---|
22 | This board uses a different clock for the Exar 88681 DUART than is |
---|
23 | documented in the Exar manual or the original MC68681 manual. This |
---|
24 | resulted in the need for the the mc68681 libchip driver to support |
---|
25 | BSP specific baud rate tables and the development of a DMV177 |
---|
26 | specific baud rate table. |
---|
27 | |
---|
28 | In the end, this all works but you have a very limited range of |
---|
29 | useful baud rates on the 88681 ports compared to what would have |
---|
30 | been supported had DY-4 just followed the Exar or Motorola manual. |
---|
31 | |
---|
32 | |
---|
33 | SCC Addresses |
---|
34 | ============= |
---|
35 | The full set of SCC addresses is not documented in the DY-4 manual |
---|
36 | and they are not ordered as one would expect. Normally the four |
---|
37 | SCC registers are ordered Control A, Data A, Control B, and Data B. |
---|
38 | DY-4 orders them with B first. |
---|
39 | |
---|
40 | This required extra time to debug. |
---|
41 | |
---|
42 | |
---|
43 | SCV64 and the Foundation Firmware |
---|
44 | ================================= |
---|
45 | DY-4 technical support did not offer code to determine which interrupt |
---|
46 | sources were pending at the SCV64. They recommended calling into the |
---|
47 | Foundation Firmware ROM monitor to figure this out. The Foundation |
---|
48 | Firmware did not recognize enough interrupts on this board to be useful. |
---|
49 | |
---|
50 | In the end, we gave up on their technical support's recommendation |
---|
51 | and directly manipulated the SVC64. This is what we wanted to do in |
---|
52 | the first place but we got no information from them to aid in this. |
---|
53 | Luckily, the manual does document enough of DY-4's mapping of the specific |
---|
54 | interrupt sources to make this work. |
---|
55 | |
---|
56 | |
---|
57 | Z85C30 SCC Clock Speed |
---|
58 | ====================== |
---|
59 | |
---|
60 | The Z85C30 SCC can be factory configured for 10 Mhz or 2.4616 Mhz. Code |
---|
61 | had to be added to dynamically determine which clock was installed. |
---|
62 | |
---|
63 | The board we had used a 10 Mhz clock. No testing was done with a 2.4616 Mhz |
---|
64 | clock. |
---|
65 | |
---|
66 | |
---|
67 | P2 Octopus Cable |
---|
68 | ================ |
---|
69 | |
---|
70 | DY-4's P2 breakout is large and a bit unwieldy. It was difficult to |
---|
71 | fight into the VME cage we used. The SCSI connector comes off the |
---|
72 | side and is very stiff thus making it difficult to route around |
---|
73 | anything in the back of the cage. We gave up on trying to use |
---|
74 | it in the first few slots of OAR's cage. |
---|