source: rtems/c/src/lib/libbsp/powerpc/beatnik/pci/motload_fixup.c @ b7a6d23a

4.104.115
Last change on this file since b7a6d23a was b7a6d23a, checked in by Till Straumann <strauman@…>, on 12/03/09 at 16:56:50
  • importing 'beatnik' BSP from SLAC repository.
  • Property mode set to 100644
File size: 6.6 KB
Line 
1/* $Id$ */
2
3/* remap the zero-based PCI IO spaces of both hoses to a single
4 * address space
5 *
6 * This must be called AFTER to BSP_pci_initialize()
7 */
8
9/*
10 * Authorship
11 * ----------
12 * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was
13 *     created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
14 *         Stanford Linear Accelerator Center, Stanford University.
15 *
16 * Acknowledgement of sponsorship
17 * ------------------------------
18 * The 'beatnik' BSP was produced by
19 *     the Stanford Linear Accelerator Center, Stanford University,
20 *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
21 *
22 * Government disclaimer of liability
23 * ----------------------------------
24 * Neither the United States nor the United States Department of Energy,
25 * nor any of their employees, makes any warranty, express or implied, or
26 * assumes any legal liability or responsibility for the accuracy,
27 * completeness, or usefulness of any data, apparatus, product, or process
28 * disclosed, or represents that its use would not infringe privately owned
29 * rights.
30 *
31 * Stanford disclaimer of liability
32 * --------------------------------
33 * Stanford University makes no representations or warranties, express or
34 * implied, nor assumes any liability for the use of this software.
35 *
36 * Stanford disclaimer of copyright
37 * --------------------------------
38 * Stanford University, owner of the copyright, hereby disclaims its
39 * copyright and all other rights in this software.  Hence, anyone may
40 * freely use it for any purpose without restriction. 
41 *
42 * Maintenance of notices
43 * ----------------------
44 * In the interest of clarity regarding the origin and status of this
45 * SLAC software, this and all the preceding Stanford University notices
46 * are to remain affixed to any copy or derivative of this software made
47 * or distributed by the recipient and are to be affixed to any copy of
48 * software made or distributed by the recipient that contains a copy or
49 * derivative of this software.
50 *
51 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
52 */
53#include <rtems.h>
54#include <bsp.h>
55#include <libcpu/io.h>
56#include <bsp/pci.h>
57#include <bsp/irq.h>
58#include <rtems/bspIo.h>
59#include <bsp/gtreg.h>
60#include "pci_io_remap.h"
61
62static int
63fixup_irq_line(int bus, int slot, int fun, void *uarg)
64{
65unsigned char line;
66        pci_read_config_byte( bus, slot, fun, PCI_INTERRUPT_LINE, &line);
67        if ( line < BSP_IRQ_GPP_0 ) {
68                pci_write_config_byte( bus, slot, fun, PCI_INTERRUPT_LINE, line + BSP_IRQ_GPP_0 );
69        }
70
71        return 0;
72}
73
74void BSP_motload_pci_fixup(void)
75{
76uint32_t        b0,b1,r0,r1,lim,dis;
77
78        /* MotLoad on the mvme5500 and mvme6100 configures the PCI
79         * busses nicely, i.e., the values read from the memory address
80         * space BARs by means of PCI config cycles directly reflect the
81         * CPU memory map. Thus, the presence of two hoses is already hidden.
82         *
83         * Unfortunately, all PCI I/O addresses are 'zero-based' i.e.,
84         * a hose-specific base address would have to be added to
85         * the values read from config space.
86         *
87         * We fix this here so I/O BARs also reflect the CPU memory map.
88         *
89         * Furthermore, the mvme5500 uses
90         *    f000.0000
91         *  ..f07f.ffff  for PCI-0 / hose0
92         *
93         *  and
94         *
95         *    f080.0000
96         *  ..f0ff.0000  for PCI-1 / hose 0
97         *
98         *  whereas the mvme6100 does it the other way round...
99         */
100
101        b0 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Low_Decode) );
102        b1 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Low_Decode) );
103
104        r0 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap) );
105        r1 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap) );
106
107        switch ( BSP_getDiscoveryVersion(0) ) {
108                case MV_64360:
109                        /* In case of the MV64360 the 'limit' is actually a 'size'!
110                         * Disable by setting special bits in the 'BAR disable reg'.
111                         */
112                        dis = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL) );
113                        /* disable PCI0 I/O and PCI1 I/O */
114                        out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis | (1<<9) | (1<<14) );
115                        /* remap busses on hose 0; if the remap register was already set, assume
116                         * that someone else [such as the bootloader] already performed the fixup
117                         */
118                        if ( (b0 & 0xffff) && 0 == (r0 & 0xffff) ) {
119                                rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xffff)<<16 );
120                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xffff) );
121                        }
122
123                        /* remap busses on hose 1 */
124                        if ( (b1 & 0xffff) && 0 == (r1 & 0xffff) ) {
125                                rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xffff)<<16 );
126                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xffff) );
127                        }
128
129                        /* re-enable */
130                        out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis );
131                break;
132
133                case GT_64260_A:
134                case GT_64260_B:
135                       
136                        if ( (b0 & 0xfff) && 0 == (r0 & 0xfff) ) { /* base are only 12 bits */
137                                /* switch window off by setting the limit < base */
138                                lim = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode) );
139                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), 0 );
140                                /* remap busses on hose 0 */
141                                rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xfff)<<20 );
142
143                                /* BTW: it seems that writing the base register also copies the
144                                 * value into the 'remap' register automatically (??)
145                                 */
146                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xfff) );
147
148                                /* re-enable */
149                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), lim );
150                        }
151
152                        if ( (b1 & 0xfff) && 0 == (r1 & 0xfff) ) { /* base are only 12 bits */
153                                /* switch window off by setting the limit < base */
154                                lim = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode) );
155                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), 0 );
156
157                                /* remap busses on hose 1 */
158                                rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xfff)<<20 );
159
160                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xfff) );
161
162                                /* re-enable */
163                                out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), lim );
164                        }
165                break;
166
167                default:
168                        BSP_panic("Unknown discovery version; switch in file: "__FILE__" not implemented (yet)");
169                break; /* never get here */
170        }
171
172        /* Fixup the IRQ lines; the mvme6100 maps them nicely into our scheme, i.e., GPP
173         * interrupts start at 64 upwards
174         *
175         * The mvme5500 is apparently initialized differently :-(. GPP interrupts start at 0
176         * Since all PCI interrupts are wired to GPP we simply check for a value < 64 and
177         * reprogram the interrupt line register.
178         */
179        BSP_pciScan(0, fixup_irq_line, 0);
180}
181
182
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