source: rtems/c/src/lib/libbsp/powerpc/beatnik/marvell/gtpcireg.h @ b7a6d23a

4.104.115
Last change on this file since b7a6d23a was b7a6d23a, checked in by Till Straumann <strauman@…>, on Dec 3, 2009 at 4:56:50 PM
  • importing 'beatnik' BSP from SLAC repository.
  • Property mode set to 100644
File size: 40.0 KB
Line 
1/*      $NetBSD: gtpcireg.h,v 1.4 2005/12/11 12:22:16 christos Exp $    */
2
3/*
4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *      This product includes software developed for the NetBSD Project by
18 *      Allegro Networks, Inc., and Wasabi Systems, Inc.
19 * 4. The name of Allegro Networks, Inc. may not be used to endorse
20 *    or promote products derived from this software without specific prior
21 *    written permission.
22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23 *    or promote products derived from this software without specific prior
24 *    written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#ifndef _DEV_GTPCIREG_H
41#define _DEV_GTPCIREG_H
42
43#define PCI__BIT(bit)                   (1U << (bit))
44#define PCI__MASK(bit)                  (PCI__BIT(bit) - 1)
45#define PCI__GEN(bus, off, num)         (((off)^((bus) << 7))+((num) << 4))
46#define PCI__EXT(data, bit, len)        (((data) >> (bit)) & PCI__MASK(len))
47#define PCI__CLR(data, bit, len)        ((data) &= ~(PCI__MASK(len) << (bit)))
48#define PCI__INS(bit, new)              ((new) << (bit))
49
50#define PCI_SYNC_REG(bus)               (0xc0 | ((bus) << 3))
51
52/*
53 * Table 185: PCI Slave ADDRess Decoding Register Map
54 */
55#define PCI_SCS0_BAR_SIZE(bus)                          PCI__GEN(bus, 0x0c08, 0)
56#define PCI_SCS2_BAR_SIZE(bus)                          PCI__GEN(bus, 0x0c0c, 0)
57#define PCI_CS0_BAR_SIZE(bus)                           PCI__GEN(bus, 0x0c10, 0)
58#define PCI_CS3_BAR_SIZE(bus)                           PCI__GEN(bus, 0x0c14, 0)
59#define PCI_SCS1_BAR_SIZE(bus)                          PCI__GEN(bus, 0x0d08, 0)
60#define PCI_SCS3_BAR_SIZE(bus)                          PCI__GEN(bus, 0x0d0c, 0)
61#define PCI_CS1_BAR_SIZE(bus)                           PCI__GEN(bus, 0x0d10, 0)
62#define PCI_BOOTCS_BAR_SIZE(bus)                        PCI__GEN(bus, 0x0d14, 0)
63#define PCI_CS2_BAR_SIZE(bus)                           PCI__GEN(bus, 0x0d18, 0)
64#define PCI_P2P_MEM0_BAR_SIZE(bus)                      PCI__GEN(bus, 0x0d1c, 0)
65#define PCI_P2P_MEM1_BAR_SIZE(bus)                      PCI__GEN(bus, 0x0d20, 0)
66#define PCI_P2P_IO_BAR_SIZE(bus)                        PCI__GEN(bus, 0x0d24, 0)
67#define PCI_CPU_BAR_SIZE(bus)                           PCI__GEN(bus, 0x0d28, 0)
68#define PCI_EXPANSION_ROM_BAR_SIZE(bus)                 PCI__GEN(bus, 0x0d2c, 0)
69#define PCI_DAC_SCS0_BAR_SIZE(bus)                      PCI__GEN(bus, 0x0e00, 0)
70#define PCI_DAC_SCS1_BAR_SIZE(bus)                      PCI__GEN(bus, 0x0e04, 0)
71#define PCI_DAC_SCS2_BAR_SIZE(bus)                      PCI__GEN(bus, 0x0e08, 0)
72#define PCI_DAC_SCS3_BAR_SIZE(bus)                      PCI__GEN(bus, 0x0e0c, 0)
73#define PCI_DAC_CS0_BAR_SIZE(bus)                       PCI__GEN(bus, 0x0e10, 0)
74#define PCI_DAC_CS1_BAR_SIZE(bus)                       PCI__GEN(bus, 0x0e14, 0)
75#define PCI_DAC_CS2_BAR_SIZE(bus)                       PCI__GEN(bus, 0x0e18, 0)
76#define PCI_DAC_CS3_BAR_SIZE(bus)                       PCI__GEN(bus, 0x0e1c, 0)
77#define PCI_DAC_BOOTCS_BAR_SIZE(bus)                    PCI__GEN(bus, 0x0e20, 0)
78#define PCI_DAC_P2P_MEM0_BAR_SIZE(bus)                  PCI__GEN(bus, 0x0e24, 0)
79#define PCI_DAC_P2P_MEM1_BAR_SIZE(bus)                  PCI__GEN(bus, 0x0e28, 0)
80#define PCI_DAC_CPU_BAR_SIZE(bus)                       PCI__GEN(bus, 0x0e2c, 0)
81#define PCI_BASE_ADDR_REGISTERS_ENABLE(bus)             PCI__GEN(bus, 0x0c3c, 0)
82#define PCI_SCS0_BASE_ADDR_REMAP(bus)                   PCI__GEN(bus, 0x0c48, 0)
83#define PCI_SCS1_BASE_ADDR_REMAP(bus)                   PCI__GEN(bus, 0x0d48, 0)
84#define PCI_SCS2_BASE_ADDR_REMAP(bus)                   PCI__GEN(bus, 0x0c4c, 0)
85#define PCI_SCS3_BASE_ADDR_REMAP(bus)                   PCI__GEN(bus, 0x0d4c, 0)
86#define PCI_CS0_BASE_ADDR_REMAP(bus)                    PCI__GEN(bus, 0x0c50, 0)
87#define PCI_CS1_BASE_ADDR_REMAP(bus)                    PCI__GEN(bus, 0x0d50, 0)
88#define PCI_CS2_BASE_ADDR_REMAP(bus)                    PCI__GEN(bus, 0x0d58, 0)
89#define PCI_CS3_BASE_ADDR_REMAP(bus)                    PCI__GEN(bus, 0x0c54, 0)
90#define PCI_ADDR_DECODE_CONTROL(bus)                    PCI__GEN(bus, 0x0d3c, 0)
91#define PCI_BOOTCS_ADDR_REMAP(bus)                      PCI__GEN(bus, 0x0d54, 0)
92#define PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus)           PCI__GEN(bus, 0x0d5c, 0)
93#define PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus)          PCI__GEN(bus, 0x0d60, 0)
94#define PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus)           PCI__GEN(bus, 0x0d64, 0)
95#define PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus)          PCI__GEN(bus, 0x0d68, 0)
96#define PCI_P2P_IO_BASE_ADDR_REMAP(bus)                 PCI__GEN(bus, 0x0d6c, 0)
97#define PCI_CPU_BASE_ADDR_REMAP(bus)                    PCI__GEN(bus, 0x0d70, 0)
98#define PCI_DAC_SCS0_BASE_ADDR_REMAP(bus)               PCI__GEN(bus, 0x0f00, 0)
99#define PCI_DAC_SCS1_BASE_ADDR_REMAP(bus)               PCI__GEN(bus, 0x0f04, 0)
100#define PCI_DAC_SCS2_BASE_ADDR_REMAP(bus)               PCI__GEN(bus, 0x0f08, 0)
101#define PCI_DAC_SCS3_BASE_ADDR_REMAP(bus)               PCI__GEN(bus, 0x0f0c, 0)
102#define PCI_DAC_CS0_BASE_ADDR_REMAP(bus)                PCI__GEN(bus, 0x0f10, 0)
103#define PCI_DAC_CS1_BASE_ADDR_REMAP(bus)                PCI__GEN(bus, 0x0f14, 0)
104#define PCI_DAC_CS2_BASE_ADDR_REMAP(bus)                PCI__GEN(bus, 0x0f18, 0)
105#define PCI_DAC_CS3_BASE_ADDR_REMAP(bus)                PCI__GEN(bus, 0x0f1c, 0)
106#define PCI_DAC_BOOTCS_BASE_ADDR_REMAP(bus)             PCI__GEN(bus, 0x0f20, 0)
107#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus)       PCI__GEN(bus, 0x0f24, 0)
108#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus)      PCI__GEN(bus, 0x0f28, 0)
109#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus)       PCI__GEN(bus, 0x0f2c, 0)
110#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus)      PCI__GEN(bus, 0x0f30, 0)
111#define PCI_DAC_CPU_BASE_ADDR_REMAP(bus)                PCI__GEN(bus, 0x0f34, 0)
112#define PCI_EXPANSION_ROM_BASE_ADDR_REMAP(bus)          PCI__GEN(bus, 0x0f38, 0)
113
114/*
115 * Table 186: PCI Control Register Map
116 */
117#define PCI_COMMAND(bus)                                PCI__GEN(bus, 0x0c00, 0)
118#define PCI_MODE(bus)                                   PCI__GEN(bus, 0x0d00, 0)
119#define PCI_TIMEOUT_RETRY(bus)                          PCI__GEN(bus, 0x0c04, 0)
120#define PCI_READ_BUFFER_DISCARD_TIMER(bus)              PCI__GEN(bus, 0x0d04, 0)
121#define PCI_MSI_TRIGGER_TIMER(bus)                      PCI__GEN(bus, 0x0c38, 0)
122#define PCI_ARBITER_CONTROL(bus)                        PCI__GEN(bus, 0x1d00, 0)
123#define PCI_INTERFACE_XBAR_CONTROL_LOW(bus)             PCI__GEN(bus, 0x1d08, 0)
124#define PCI_INTERFACE_XBAR_CONTROL_HIGH(bus)            PCI__GEN(bus, 0x1d0c, 0)
125#define PCI_INTERFACE_XBAR_TIMEOUT(bus)                 PCI__GEN(bus, 0x1d04, 0)
126#define PCI_READ_RESPONSE_XBAR_CONTROL_LOW(bus)         PCI__GEN(bus, 0x1d18, 0)
127#define PCI_READ_RESPONSE_XBAR_CONTROL_HIGH(bus)        PCI__GEN(bus, 0x1d1c, 0)
128#define PCI_SYNC_BARRIER(bus)                           PCI__GEN(bus, 0x1d10, 0)
129#define PCI_P2P_CONFIGURATION(bus)                      PCI__GEN(bus, 0x1d14, 0)
130#define PCI_P2P_SWAP_CONTROL(bus)                       PCI__GEN(bus, 0x1d54, 0)
131#define PCI_ACCESS_CONTROL_BASE_LOW(bus, n)             PCI__GEN(bus, 0x1e00, n)
132#define PCI_ACCESS_CONTROL_BASE_HIGH(bus, n)            PCI__GEN(bus, 0x1e04, n)
133#define PCI_ACCESS_CONTROL_TOP(bus, n)                  PCI__GEN(bus, 0x1e08, n)
134
135
136/*
137 * Table 187: PCI Snoop Control Register Map
138 */
139#define PCI_SNOOP_CONTROL_BASE_LOW(bus, n)              PCI__GEN(bus, 0x1f00, n)
140#define PCI_SNOOP_CONTROL_BASE_HIGH(bus, n)             PCI__GEN(bus, 0x1f04, n)
141#define PCI_SNOOP_CONTROL_TOP(bus, n)                   PCI__GEN(bus, 0x1f08, n)
142
143/*
144 * Table 188: PCI Configuration ACCESS_Register Map
145 */
146#define PCI_CONFIG_ADDR(bus)                            PCI__GEN(bus, 0x0cf8, 0)
147#define PCI_CONFIG_DATA(bus)                            PCI__GEN(bus, 0x0cfc, 0)
148#define PCI_INTR_ACK(bus)                               PCI__GEN(bus, 0x0c34, 0)
149
150/*
151 * Table 189: PCI ERROR Report Register Map
152 */
153#define PCI_SERR_MASK(bus)                              PCI__GEN(bus, 0x0c28, 0)
154#define PCI_ERROR_ADDRESS_LOW(bus)                      PCI__GEN(bus, 0x1d40, 0)
155#define PCI_ERROR_ADDRESS_HIGH(bus)                     PCI__GEN(bus, 0x1d44, 0)
156#define PCI_ERROR_DATA_LOW(bus)                         PCI__GEN(bus, 0x1d48, 0)
157#define PCI_ERROR_DATA_HIGH(bus)                        PCI__GEN(bus, 0x1d4c, 0)
158#define PCI_ERROR_COMMAND(bus)                          PCI__GEN(bus, 0x1d50, 0)
159#define PCI_ERROR_CAUSE(bus)                            PCI__GEN(bus, 0x1d58, 0)
160#define PCI_ERROR_MASK(bus)                             PCI__GEN(bus, 0x1d5c, 0)
161
162
163
164/*
165 * Table 223: PCI Base Address Registers Enable
166 * If a bit is clear, the BAR is enabled.  If set, disabled.  The GT64260]
167 * prevents disabling both memory mapped and I/O mapped BARs (bits 9 and 10
168 * cannot simultaneously be set to 1).
169 */
170#define PCI_BARE_SCS0En         PCI__BIT(0)     /* SCS[0]* BAR Enable */
171#define PCI_BARE_SCS1En         PCI__BIT(1)     /* SCS[1]* BAR Enable */
172#define PCI_BARE_SCS2En         PCI__BIT(2)     /* SCS[2]* BAR Enable */
173#define PCI_BARE_SCS3En         PCI__BIT(3)     /* SCS[3]* BAR Enable */
174#define PCI_BARE_CS0En          PCI__BIT(4)     /* CS[0]* BAR Enable */
175#define PCI_BARE_CS1En          PCI__BIT(5)     /* CS[1]* BAR Enable */
176#define PCI_BARE_CS2En          PCI__BIT(6)     /* CS[2]* BAR Enable */
177#define PCI_BARE_CS3En          PCI__BIT(7)     /* CS[3]* BAR Enable */
178#define PCI_BARE_BootCSEn       PCI__BIT(8)     /* BootCS* BAR Enable */
179#define PCI_BARE_IntMemEn       PCI__BIT(9)     /* Memory Mapped Internal
180                                                 * Registers BAR Enable */
181#define PCI_BARE_IntIOEn        PCI__BIT(10)    /* I/O Mapped Internal
182                                                 * Registers BAR Enable */
183#define PCI_BARE_P2PMem0En      PCI__BIT(11)    /* P2P Mem0 BAR Enable */
184#define PCI_BARE_P2PMem1En      PCI__BIT(12)    /* P2P Mem1 BAR Enable */
185#define PCI_BARE_P2PIOEn        PCI__BIT(13)    /* P2P IO BAR Enable */
186#define PCI_BARE_CPUEn          PCI__BIT(14)    /* CPU BAR Enable */
187#define PCI_BARE_DSCS0En        PCI__BIT(15)    /* DAC SCS[0]* BAR Enable */
188#define PCI_BARE_DSCS1En        PCI__BIT(16)    /* DAC SCS[1]* BAR Enable */
189#define PCI_BARE_DSCS2En        PCI__BIT(17)    /* DAC SCS[2]* BAR Enable */
190#define PCI_BARE_DSCS3En        PCI__BIT(18)    /* DAC SCS[3]* BAR Enable */
191#define PCI_BARE_DCS0En         PCI__BIT(19)    /* DAC CS[0]* BAR Enable */
192#define PCI_BARE_DCS1En         PCI__BIT(20)    /* DAC CS[1]* BAR Enable */
193#define PCI_BARE_DCS2En         PCI__BIT(21)    /* DAC CS[2]* BAR Enable */
194#define PCI_BARE_DCS3En         PCI__BIT(22)    /* DAC CS[3]* BAR Enable */
195#define PCI_BARE_DBootCSEn      PCI__BIT(23)    /* DAC BootCS* BAR Enable */
196#define PCI_BARE_DP2PMem0En     PCI__BIT(24)    /* DAC P2P Mem0 BAR Enable */
197#define PCI_BARE_DP2PMem1En     PCI__BIT(25)    /* DAC P2P Mem1 BAR Enable */
198#define PCI_BARE_DCPUEn         PCI__BIT(26)    /* DAC CPU BAR Enable */
199
200/*
201 * Table 254: PCI Address Decode Control
202 * Bits 7:4 and 31:25 are reserved
203 * 00:00 RemapWrDis             Address Remap Registers Write Disable
204 *                              0: Writes to a BAR result in updating the
205 *                                 corresponding remap register with the BAR's
206 *                                 new value.
207 *                              1: Writes to a BAR have no affect on the
208 *                                 corresponding Remap register value.
209 * 01:01 ExpRomDev              Expansion ROM Device (0: CS[3]; 1: BootCS)
210 * 02:02 VPDDev                 VPD Device (0: CS[3]; 1: BootCS)
211 * 03:03 MsgAcc                 Messaging registers access
212 *                              0: Messaging unit registers are accessible on
213 *                                 lowest 4Kbyte of SCS[0] BAR space.
214 *                              1: Messaging unit registers are only accessible
215 *                                 as part of the GT64260 internal space.
216 * 07:04 Reserved
217 * 24:08 VPDHighAddr            VPD High Address bits
218 *                              [31:15] of VPD the address.
219 * 31:25 Reserved
220 */
221#define PCI_ADC_RemapWrDis              PCI__BIT(0)
222#define PCI_ADC_ExpRomDev               PCI__BIT(1)
223#define PCI_ADC_VPDDev                  PCI__BIT(2)
224#define PCI_ADC_MsgAcc                  PCI__BIT(3)
225#define PCI_ADC_VPDHighAddr_GET(v)      PCI__EXT(v, 8, 16)
226
227
228/*
229 * Table 255: PCI Command
230 * 00:00 MByteSwap      PCI Master Byte Swap
231 *                              NOTE: GT-64120 and GT-64130 compatible.
232 *                      When set to 0, the GTO64260 PCI master swaps the bytes
233 *                      of the incoming and outgoing PCI data (swap the 8 bytes
234 *                      of a longword).
235 * 01:01 Reserved
236 * 02:02 Reserved       Must be 0.
237 * 03:03 Reserved
238 * 04:04 MWrCom         PCI Master Write Combine Enable
239 *                      When set to 1, write combining is enabled.
240 * 05:05 MRdCom         PCI Master Read Combine Enable
241 *                      When set to 1, read combining is enabled.
242 * 06:06 MWrTrig        PCI Master Write Trigger
243 *                      0: Accesses the PCI bus only when the whole burst is
244 *                         written into the master write buffer.
245 *                      1: Accesses the PCI bus when the first data is written
246 *                         into the master write buffer.
247 * 07:07 MRdTrig        PCI Master Read Trigger
248 *                      0: Returns read data to the initiating unit only when
249 *                         the whole burst is written into master read buffer.
250 *                      1: Returns read data to the initiating unit when the
251 *                         first read data is written into master read buffer.
252 * 08:08 MRdLine        PCI Master Memory Read Line Enable
253 *                      (0: Disable; 1: Enable)
254 * 09:09 MRdMul         PCI Master Memory Read Multiple Enable
255 *                      (0: Disable; 1: Enable)
256 * 10:10 MWordSwap      PCI Master Word Swap
257 *                              NOTE: GT-64120 and GT-64130 compatible.
258 *                      When set to 1, the GT64260 PCI master swaps the 32-bit
259 *                      words of the incoming and outgoing PCI data.
260 * 11:11 SWordSwap      PCI Slave Word Swap
261 *                              NOTE: GT-64120 and GT-64130 compatible.
262 *                      When set to 1, the GT64260 PCI slave swaps the 32-bit
263 *                      words of the incoming and outgoing PCI data.
264 * 12:12 IntBusCtl      PCI Interface Unit Internal Bus Control
265 *                              NOTE: Reserved for Galileo Technology usage
266 *                      0: Enable internal bus sharing between master and
267 *                         slave interfaces.
268 *                      1: Disable internal bus sharing between master and
269 *                         slave interfaces.
270 * 13:13 SBDis          PCI Slave Sync Barrier Disable
271 *                      When set to 1, the PCI configuration read transaction
272 *                      will stop act as sync barrier transaction.
273 * 14:14 Reserved       Must be 0
274 * 15:15 MReq64         PCI Master REQ64* Enable (0: Disable; 1: Enable)
275 * 16:16 SByteSwap      PCI Slave Byte Swap
276 *                              NOTE: GT-64120 and GT-64130 compatible.
277 *                      When set to 0, the GT64260 PCI slave swaps the bytes of
278 *                      the incoming and outgoing PCI data (swap the 8 bytes of
279 *                      a long-word).
280 * 17:17 MDACEn         PCI Master DAC Enable
281 *                      0: Disable (The PCI master never drives the DAC cycle)
282 *                      1: Enable (In case the upper 32-bit address is not 0,
283 *                         the PCI master drives the DAC cycle)
284 * 18:18 M64Allign      PCI Master REQ64* assertion on non-aligned
285 *                      0: Disable (The master asserts REQ64* only if
286 *                         the address is 64-bit aligned)
287 *                      1: Enable (The master asserts REQ64* even if
288 *                         the address is not 64-bit aligned)
289 * 19:19 PErrProp       Parity/ECC Errors Propagation Enable
290 *                      0: Disable (The PCI interface always drives
291 *                         correct parity on the PAR signal)
292 *                      1: Enable (In case of slave read bad ECC from
293 *                         SDRAM, or master write with bad parity/ECC
294 *                         indication from the initiator, the PCI interface
295 *                         drives bad parity on the PAR signal)
296 * 20:20 SSwapEn        PCI Slave Swap Enable
297 *                              NOTE: Even if the SSwapEn bit is set to 1 and
298 *                              the PCI address does not match any of the
299 *                              Access Control registers, slave data swapping
300 *                              works according to SByteSwap and SWordSwap bits.
301 *                      0: PCI slave data swapping is determined via
302 *                         SByteSwap and SWordSwap bits (bits 16 and 11),
303 *                         as in the GT-64120/130.
304 *                      1: PCI slave data swapping is determined via PCISwap
305 *                         bits [25:24] in the PCI Access Control registers.
306 * 21:21 MSwapEn        PCI Master Swap Enable
307 *                      0: PCI master data swapping is determined via
308 *                         MByteSwap and MWordSwap bits (bits 0 and 10),
309 *                         as in the GT-64120/130.
310 *                      1: PCI master data swapping is determined via
311 *                         PCISwap bits in CPU to PCI Address Decoding
312 *                         registers.
313 * 22:22 MIntSwapEn     PCI Master Configuration Transactions Data Swap Enable
314 *                              NOTE: Reserved for Galileo Technology usage.
315 *                      0: Disable (The PCI master configuration transaction
316 *                         to the PCI bus is always in Little Endian convention)
317 *                      1: Enable (The PCI master configuration transaction to
318 *                         the PCI bus is determined according to the setting
319 *                         of MSwapEn bit)
320 * 23:23 LBEn           PCI Loop Back Enable
321 *                              NOTE: Reserved for Galileo Technology usage.
322 *                      0: Disable (The PCI slave does not respond to
323 *                         transactions initiated by the PCI master)
324 *                      1: Enable (The PCI slave does respond to
325 *                         transactions initiated by the PCI master,
326 *                         if targeted to the slave (address match)
327 * 26:24 SIntSwap       PCI Slave data swap control on PCI accesses to the
328 *                      GT64260 internal and configuration registers.
329 *                      Bits encoding are the same as bits[26:24] in PCI Access
330 *                      Control registers.
331 * 27:27 Reserved       Must be 0.
332 * 31:28 Reserved       Read only.
333 */
334#define PCI_CMD_MByteSwap       PCI__BIT(0)
335#define PCI_CMD_MBZ0_2          PCI__BIT(2)
336#define PCI_CMD_MWrCom          PCI__BIT(4)
337#define PCI_CMD_MRdCom          PCI__BIT(5)
338#define PCI_CMD_MWrTrig         PCI__BIT(6)
339#define PCI_CMD_MRdTrig         PCI__BIT(7)
340#define PCI_CMD_MRdLine         PCI__BIT(8)
341#define PCI_CMD_MRdMul          PCI__BIT(9)
342#define PCI_CMD_MWordSwap       PCI__BIT(10)
343#define PCI_CMD_SWordSwap       PCI__BIT(11)
344#define PCI_CMD_IntBusCtl       PCI__BIT(12)
345#define PCI_CMD_SBDis           PCI__BIT(13)
346#define PCI_CMD_MBZ0_14         PCI__BIT(14)
347#define PCI_CMD_MReq64          PCI__BIT(15)
348#define PCI_CMD_SByteSwap       PCI__BIT(16)
349#define PCI_CMD_MDCAEn          PCI__BIT(17)
350#define PCI_CMD_M64Allign       PCI__BIT(18)
351#define PCI_CMD_PErrProp        PCI__BIT(19)
352#define PCI_CMD_SSwapEn         PCI__BIT(20)
353#define PCI_CMD_MSwapEn         PCI__BIT(21)
354#define PCI_CMD_MIntSwapEn      PCI__BIT(22)
355#define PCI_CMD_LBEn            PCI__BIT(23)
356#define PCI_CMD_SIntSwap_GET(v) PCI__EXT(v, 24, 3)
357#define PCI_CMD_MBZ0_27         PCI__BIT(27)
358
359
360/*
361 * Table 256: PCI Mode
362 * 00:00 PciID          PCI Interface ID -- Read Only (PCI_0: 0x0; PCI_1: 0x1)
363 * 01:01 Reserved
364 * 02:02 Pci64          64-bit PCI Interface -- Read Only
365 *                      When set to 1, the PCI interface is configured to a
366 *                      64 bit interface.
367 * 07:03 Reserved
368 * 08:08 ExpRom         Expansion ROM Enable -- Read Only from PCI
369 *                      When set to 1, the expansion ROM BAR is enabled.
370 * 09:09 VPD            VPD Enable -- Read Only from PCI
371 *                      When set to 1, VPD is supported.
372 * 10:10 MSI            MSI Enable -- Read Only from PCI
373 *                      When set to 1, MSI is supported.
374 * 11:11 PMG            Power Management Enable -- Read Only from PCI
375 *                      When set to 1, PMG is supported.
376 * 12:12 HotSwap        CompactPCI Hot Swap Enable -- Read Only from PCI
377 *                      When set to 1, HotSwap is supported.
378 * 13:13 BIST           BIST Enable -- Read only from PCI
379 *                      If set to 1, BIST is enabled.
380 * 30:14 Reserved
381 * 31:31 PRst           PCI Interface Reset Indication -- Read Only
382 *                      Set to 0 as long as the RST* pin is asserted.
383 */
384#define PCI_MODE_PciID_GET(v)   PCI__EXT(v, 0, 1)
385#define PCI_MODE_Pci64          PCI__BIT(2)
386#define PCI_MODE_ExpRom         PCI__BIT(8)
387#define PCI_MODE_VPD            PCI__BIT(9)
388#define PCI_MODE_MSI            PCI__BIT(10)
389#define PCI_MODE_PMG            PCI__BIT(11)
390#define PCI_MODE_HotSwap        PCI__BIT(12)
391#define PCI_MODE_BIST           PCI__BIT(13)
392#define PCI_MODE_PRst           PCI__BIT(31)
393
394/*
395 * Table 257: PCI Timeout and Retry
396 * 07:00 Timeout0       Specifies the number of PClk cycles the GT64260 slave
397 *                      holds the PCI bus before terminating a transaction
398 *                      with RETRY.
399 * 15:08 Timeout1       Specifies the number of PClk cycles the GT64260 slave
400 *                      holds the PCI bus before terminating a transaction
401 *                      with DISCONNECT.
402 * 23:16 RetryCtr       Retry Counter
403 *                      Specifies the number of retries of the GT64260 Master.
404 *                      The GT64260 generates an interrupt when this timer
405 *                      expires.  A 0x00 value means a retry forever.
406 * 31:24 Reserved
407 */
408#define PCI_TMORTRY_Timeout0_GET(v)     PCI__EXT(v, 0, 8)
409#define PCI_TMORTRY_Timeout1_GET(v)     PCI__EXT(v, 8, 8)
410#define PCI_TMORTRY_RetryCtr_GET(v)     PCI__EXT(v, 16, 8)
411
412
413/*
414 * Table 258: PCI Read Buffer Discard Timer
415 * 15:00 Timer          Specifies the number of PClk cycles the GT64260
416 *                      slave keeps an non-accessed read buffers (non com-
417 *                      pleted delayed read) before invalidating the buffer.
418 * 23:16 RdBufEn        Slave Read Buffers Enable
419 *                      Each bit corresponds to one of the eight read buffers.
420 *                      If set to 1, buffer is enabled.
421 * 31:24 Reserved
422 */
423#define PCI_RdBufDisTmr_Timer_GET(v)    PCI__EXT(v, 0, 16)
424#define PCI_RdBufDisTmr_RdBufEn_GET(v)  PCI__EXT(v, 16, 8)
425#define PCI_RdBufDisTmr_RdBufEn0(v)     PCI__BIT(16)
426#define PCI_RdBufDisTmr_RdBufEn1(v)     PCI__BIT(17)
427#define PCI_RdBufDisTmr_RdBufEn2(v)     PCI__BIT(18)
428#define PCI_RdBufDisTmr_RdBufEn3(v)     PCI__BIT(19)
429#define PCI_RdBufDisTmr_RdBufEn4(v)     PCI__BIT(20)
430#define PCI_RdBufDisTmr_RdBufEn5(v)     PCI__BIT(21)
431#define PCI_RdBufDisTmr_RdBufEn6(v)     PCI__BIT(22)
432#define PCI_RdBufDisTmr_RdBufEn7(v)     PCI__BIT(23)
433
434/*
435 * Table 259: MSI Trigger Timer
436 * 15:00 Timer          Specifies the number of TClk cycles between consecutive
437 *                      MSI requests.
438 * 31:16 Reserved
439 */
440#define PCI_MSITrigger_Timer_GET(v)     PCI__EXT(v, 0, 16)
441
442/*
443 * Table 260: PCI Arbiter Control
444 *      NOTE:   If HPPV (bits [28:21]) is set to 0 and PAEn is set to 1,
445 *              priority scheme is reversed. This means that high priority
446 *              requests are granted if no low priority request is pending.
447 * 00:00 Reserved       Must be 0. 0x0
448 * 01:01 BDEn           Broken Detection Enable
449 *                      If set to 1, broken master detection is enabled. A mas-
450 *                      ter is said to be broken if it fails to respond to grant
451 *                      assertion within a window specified in BV (bits [6:3]).
452 * 02:02 PAEn           Priority Arbitration Enable
453 *                      0: Low priority requests are granted only when no high
454 *                         priority request is pending
455 *                      1: Weighted round robin arbitration is performed
456 *                         between high priority and low priority groups.
457 * 06:03 BV             Broken Value
458 *                      This value sets the maximum number of cycles that the
459 *                      arbiter waits for a PCI master to respond to its grant
460 *                      assertion. If a PCI master fails to assert FRAME* within
461 *                      this time, the PCI arbiter aborts the transaction and
462 *                      performs a new arbitration cycle and a maskable
463 *                      interrupt is generated. Must be greater than 0.
464 *                      NOTE:   The PCI arbiter waits for the current
465 *                              transaction to end before starting to
466 *                              count the wait-for-broken cycles.
467 *                      Must be greater than 1 for masters that performs address
468 *                      stepping (such as the GTO 64260 PCI master), since they
469 *                      require GNT* assertion for two cycles.
470 * 13:07 P[6:0]         Priority
471 *                      These bits assign priority levels to the requests
472 *                      connected to the PCI arbiter. When a PM bit is set to
473 *                      1, priority of the associated request is high.  The
474 *                      mapping between P[6:0] bits and the request/grant pairs
475 *                      are as follows:
476 *                       P[0]: internal PCI master      P[1]: external REQ0/GNT0
477 *                       P[2]: external REQ1/GNT1       P[3]: external REQ2/GNT2
478 *                       P[4]: external REQ3/GNT3       P[5]: external REQ4/GNT4
479 *                       P[6]: external REQ5/GNT5
480 * 20:14 PD[6:0]        Parking Disable
481 *                      Use these bits to disable parking on any of the PCI
482 *                      masters.  When a PD bit is set to 1, parking on the
483 *                      associated PCI master is disabled.
484 *                      NOTE:   The arbiter parks on the last master granted
485 *                              unless disabled through the PD bit. Also, if
486 *                              PD bits are all 1, the PCI arbiter parks on
487 *                              the internal PCI master.
488 * 28:21 HPPV           High Priority Preset Value
489 *                      This is the preset value of the high priority counter
490 *                      (High_cnt). This counter decrements each time a high
491 *                      priority request is granted. When the counter reaches
492 *                      zero, it reloads with this preset value.  The counter
493 *                      reloads when a low priority request is granted.
494 * 30:29 Reserved
495 * 31:31 EN             Enable
496 *                      Setting this bit to 1 enables operation of the arbiter.
497 */
498#define PCI_ARBCTL_MBZ0_0               PCI__BIT(0)
499#define PCI_ARBCTL_BDEn                 PCI__BIT(1)
500#define PCI_ARBCTL_PAEn                 PCI__BIT(2)
501#define PCI_ARBCTL_BV_GET(v)            PCI__EXT(v, 3, 4)
502#define PCI_ARBCTL_P_GET(v)             PCI__EXT(v, 7, 7)
503#define PCI_ARBCTL_PD_GET(v)            PCI__EXT(v, 14, 7)
504#define PCI_ARBCTL_HPPV_GET(v)          PCI__EXT(v, 21, 7)
505#define PCI_ARBCTL_EN                   PCI__BIT(31)
506
507#define PCI_ARBPRI_IntPci               PCI__BIT(0)
508#define PCI_ARBPRI_ExtReqGnt0           PCI__BIT(1)
509#define PCI_ARBPRI_ExtReqGnt1           PCI__BIT(2)
510#define PCI_ARBPRI_EXtReqGnt2           PCI__BIT(3)
511#define PCI_ARBPRI_EXtReqGnt3           PCI__BIT(4)
512#define PCI_ARBPRI_EXtReqGnt4           PCI__BIT(5)
513#define PCI_ARBPRI_EXtReqGnt5           PCI__BIT(6)
514
515/*
516 * Table 261: PCI Interface Crossbar Control (Low)
517 * 03:00 Arb0           Slice 0 of PCI master pizza arbiter.
518 * 07:04 Arb1           Slice 1 of PCI master pizza arbiter.
519 * 11:08 Arb2           Slice 2 of PCI master pizza arbiter.
520 * 15:12 Arb3           Slice 3 of PCI master pizza arbiter.
521 * 19:16 Arb4           Slice 4 of PCI master pizza arbiter.
522 * 23:20 Arb5           Slice 5 of PCI master pizza arbiter.
523 * 27:24 Arb6           Slice 6 of PCI master pizza arbiter.
524 * 31:28 Arb7           Slice 7 of PCI master pizza arbiter.
525 */
526#define PCI_IFXBRCTL_GET_SLICE(v, n)    PCI__EXT(v, (n) * 4, 4)
527#define PCI_IFXBRCTL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\
528                                                (v) |= PCI__INS((n)*4, s)))
529
530/*
531 * Table 262: PCI Interface Crossbar Control (High)
532 * 03:00 Arb8           Slice 8 of PCI master pizza arbiter.
533 * 07:04 Arb9           Slice 9 of PCI master pizza arbiter.
534 * 11:08 Arb10          Slice 10 of PCI master pizza arbiter.
535 * 15:12 Arb11          Slice 11 of PCI master pizza arbiter.
536 * 19:16 Arb12          Slice 12 of PCI master pizza arbiter.
537 * 23:20 Arb13          Slice 13 of PCI master pizza arbiter.
538 * 27:24 Arb14          Slice 14 of PCI master pizza arbiter.
539 * 31:28 Arb15          Slice 15 of PCI master pizza arbiter.
540 */
541#define PCI_IFXBRCH_GET_SLICE(v, n)     PCI__EXT(v, ((n) - 8) * 4, 4)
542#define PCI_IFXBRCH_SET_SLICE(v, n, s)  ((void)(PCI__CLR(v, ((n)*-8)4, 4),\
543                                                (v) |= PCI__INS(((n)-8)*4, s)))
544
545/*
546 * Table 263: PCI Interface Crossbar Timeout
547                (NOTE: Reserved for Galileo Technology usage.)
548 * 07:00 Timeout        Crossbar Arbiter Timeout Preset Value
549 * 15:08 Reserved
550 * 16:16 TimeoutEn      Crossbar Arbiter Timer Enable (1: Disable)
551 * 31:17 Reserved
552 */
553#define PCI_IFXBRTMO_Timeout_GET(v)     PCI__EXT(v, 0, 8)
554#define PCI_IFXBRTMO_TimeoutEn          PCI__BIT(16)
555
556/*
557 * Table 264: PCI Read Response Crossbar Control (Low)
558 * 03:00 Arb0           Slice 0 of PCI slave pizza arbiter.
559 * 07:04 Arb1           Slice 1 of PCI slave pizza arbiter.
560 * 11:08 Arb2           Slice 2 of PCI slave pizza arbiter.
561 * 15:12 Arb3           Slice 3 of PCI slave pizza arbiter.
562 * 19:16 Arb4           Slice 4 of PCI slave pizza arbiter.
563 * 23:20 Arb5           Slice 5 of PCI slave pizza arbiter.
564 * 27:24 Arb6           Slice 6 of PCI slave pizza arbiter.
565 * 31:28 Arb7           Slice 7 of PCI slave pizza arbiter.
566 */
567#define PCI_RRXBRCL_GET_SLICE(v, n)     PCI__EXT(v, (n) * 4, 4)
568#define PCI_RRXBRCL_SET_SLICE(v, n, s)  ((void)(PCI__CLR(v, (n)*4, 4),\
569                                                (v) |= PCI__INS((n)*4, s)))
570
571
572/*
573 * Table 265: PCI Read Response Crossbar Control (High)
574 * 03:00 Arb8           Slice 8 of PCI slave pizza arbiter.
575 * 07:04 Arb9           Slice 9 of PCI slave pizza arbiter.
576 * 11:08 Arb10          Slice 10 of PCI slave pizza arbiter.
577 * 15:12 Arb11          Slice 11 of PCI slave pizza arbiter.
578 * 19:16 Arb12          Slice 12 of PCI slave pizza arbiter.
579 * 23:20 Arb13          Slice 13 of PCI slave pizza arbiter.
580 * 27:24 Arb14          Slice 14 of PCI slave pizza arbiter.
581 * 31:28 Arb15          Slice 15 of PCI slave pizza arbiter.
582 */
583#define PCI_RRXBRCH_GET_SLICE(v, n)     PCI__EXT(v, ((n) - 8) * 4, 4)
584#define PCI_RRXBRCH_SET_SLICE(v, n, s)  ((void)(PCI__CLR(v, ((n)*-8)4, 4),\
585                                                (v) |= PCI__INS(((n)-8)*4, s)))
586
587/*
588 * Table 266: PCI Sync Barrier Virtual Register
589 * 31:0 SyncReg Sync Barrier Virtual Register
590 * PCI read from this register results in PCI slave sync barrier
591 * action.  The returned data is un-deterministic.  Read Only.
592 */
593
594/*
595 * Table 267: PCI P2P Configuration
596 * 07:00 2ndBusL        Secondary PCI Interface Bus Range Lower Boundary
597 * 15:08 2ndBusH        Secondary PCI Interface Bus Range Upper Boundary
598 * 23:16 BusNum         The PCI bus number to which the PCI interface
599 *                      is connected.
600 * 28:24 DevNum         The PCI interface's device number.
601 * 31:29 Reserved       Reserved.
602 */
603#define PCI_P2PCFG_2ndBusL_GET(v)       PCI__EXT(v,  0, 8)
604#define PCI_P2PCFG_2ndBusH_GET(v)       PCI__EXT(v,  8, 8)
605#define PCI_P2PCFG_BusNum_GET(v)        PCI__EXT(v, 16, 8)
606#define PCI_P2PCFG_DevNum_GET(v)        PCI__EXT(v, 24, 5)
607
608/*
609 * Table 268: PCI P2P Swap Control
610 * 02:00 M0Sw           P2P Mem0 BAR Swap Control
611 * 03:03 M0Req64        P2P Mem0 BAR Force REQ64
612 * 06:04 M1Sw           P2P Mem1 BAR Swap Control
613 * 07:07 M1Req64        P2P Mem1 BAR Force REQ64
614 * 10:08 DM0Sw          P2P DAC Mem0 BAR Swap Control
615 * 11:11 DM0Req64       P2P DAC Mem0 BAR Force REQ64
616 * 14:12 DM1Sw          P2P DAC Mem1 BAR Swap Control
617 * 15:15 DM1Req64       P2P DAC Mem1 BAR Force REQ64
618 * 18:16 IOSw           P2P I/O BAR Swap Control
619 * 19:19 Reserved
620 * 22:20 CfgSw          P2P Configuration Swap Control
621 * 31:19 Reserved
622 */
623#define PCI_P2PSWAP_M0Sw_GET(v)         PCI__EXT(v, 0, 3)
624#define PCI_P2PSWAP_M0Req64             PCI__BIT(3)
625#define PCI_P2PSWAP_M1Sw_GET(v)         PCI__EXT(v, 4, 3)
626#define PCI_P2PSWAP_M1Req64             PCI__BIT(7)
627#define PCI_P2PSWAP_DM0Sw_GET(v)        PCI__EXT(v, 8, 3)
628#define PCI_P2PSWAP_DM0Req64            PCI__BIT(11)
629#define PCI_P2PSWAP_DM1Sw_GET(v)        PCI__EXT(v, 12, 3)
630#define PCI_P2PSWAP_DM1Req64            PCI__BIT(15)
631#define PCI_P2PSWAP_CfgSw_GET(v)        PCI__EXT(v, 20, 3)
632
633
634
635/*
636 * Table 269: PCI Access Control Base (Low)
637 * 11:00 Addr           Base Address Corresponds to address bits[31:20].
638 * 12:12 PrefetchEn     Read Prefetch Enable
639 *                      0: Prefetch disabled (The PCI slave reads single words)
640 *                      1: Prefetch enabled.
641 * 14:14 Reserved        Must be 0
642 * 15:15 Reserved
643 * 16:16 RdPrefetch     PCI Read Aggressive Prefetch Enable; 0: Disable;
644 *                      1: Enable (The PCI slave prefetches two
645 *                      bursts in advance)
646 * 17:17 RdLinePrefetch PCI Read Line Aggressive Prefetch Enable; 0: Disable;
647 *                      1: Enable (PCI slave prefetch two bursts in advance)
648 * 18:18 RdMulPrefetch  PCI Read Multiple Aggressive Prefetch Enable
649 *                      0: Disable; 1: Enable (PCI slave prefetch two bursts in
650 *                      advance)
651 * 19:19 Reserved
652 * 21:20 MBurst         PCI Max Burst
653 *                      Specifies the maximum burst size for a single transac-
654 *                      tion between a PCI slave and the other interfaces
655 *                              00 - 4 64-bit words
656 *                              01 - 8 64-bit words
657 *                              10 - 16 64-bit words
658 *                              11 - Reserved
659 * 23:22 Reserved
660 * 25:24 PCISwap        Data Swap Control
661 *                              00 - Byte Swap
662 *                              01 - No swapping
663 *                              10 - Both byte and word swap
664 *                              11 - Word swap
665 * 26:26 Reserved       Must be 0
666 * 27:27 Reserved
667 * 28:28 AccProt        Access Protect (0: PCI access is allowed; 1; Region is
668                        not accessible from PCI)
669 * 29:29 WrProt         Write Protect (0: PCI write is allowed; 1: Region is
670 *                      not writeable from PCI)
671 * 31:30 Reserved
672 */
673#define PCI_ACCCTLBASEL_Addr_GET(v)     PCI__EXT(v, 0, 12)
674#define PCI_ACCCTLBASEL_PrefetchEn      PCI__BIT(12)
675#define PCI_ACCCTLBASEL_MBZ0_14         PCI__BIT(14)
676#define PCI_ACCCTLBASEL_RdPrefetch      PCI__BIT(16)
677#define PCI_ACCCTLBASEL_RdLinePrefetch  PCI__BIT(17)
678#define PCI_ACCCTLBASEL_RdMulPrefetch   PCI__BIT(18)
679#define PCI_ACCCTLBASEL_WBurst          PCI__EXT(v, 20, 2)
680#define PCI_ACCCTLBASEL_WBurst_8_QW     PCI__INS(20, PCI_WBURST_8_QW)
681#define PCI_ACCCTLBASEL_PCISwap         PCI__EXT(v, 24, 2)
682#define PCI_ACCCTLBASEL_PCISwap_NoSwap  PCI__INS(24, PCI_PCISWAP_NoSwap)
683#define PCI_ACCCTLBASEL_MBZ0_26         PCI__BIT(26)
684#define PCI_ACCCTLBASEL_AccProt         PCI__BIT(28)
685#define PCI_ACCCTLBASEL_WrProt          PCI__BIT(29)
686
687#define PCI_WBURST_4_QW                 0x00
688#define PCI_WBURST_8_QW                 0x01
689#define PCI_WBURST_16_QW                0x02
690#define PCI_WBURST_Reserved             0x04
691
692#define PCI_PCISWAP_ByteSwap            0x00
693#define PCI_PCISWAP_NoSwap              0x01
694#define PCI_PCISWAP_ByteWordSwap        0x02
695#define PCI_PCISWAP_WordSwap            0x04
696
697/*
698 * Table 293: PCI Snoop Control Base (Low)
699 * 11:00 Addr           Base Address     Corresponds to address bits[31:20].
700 * 13:12 Snoop          Snoop Type
701 * 31:14 Reserved
702 */
703#define PCI_SNOOPCTL_ADDR(v)    PCI__EXT(v, 0, 12)
704#define PCI_SNOOPCTL_TYPE(v)    PCI__EXT(v, 12, 2)
705
706#define PCI_SNOOP_None          0       /* no snoop */
707#define PCI_SNOOP_WT            1       /* Snoop to WT region */
708#define PCI_SNOOP_WB            2       /* Snoop to WB region */
709
710
711/*
712 * Table 305: PCI Configuration Address
713 *
714 * 07:02 RegNum         Register number.
715 * 10:08 FunctNum       Function number.
716 * 15:11 DevNum         Device number.
717 * 23:16 BusNum         Bus number.
718 * 31:31 ConfigEn       When set, an access to the Configuration Data
719 *                      register is translated into a Configuration
720 *                      or Special cycle on the PCI bus.
721 */
722#define PCI_CFG_MAKE_TAG(bus, dev, fun, reg)    (PCI__BIT(31)|\
723                                                 PCI__INS(16, (bus))|\
724                                                 PCI__INS(11, (dev))|\
725                                                 PCI__INS( 8, (fun))|\
726                                                 PCI__INS( 0, (reg)))
727#define PCI_CFG_GET_BUSNO(tag)                  PCI__EXT(tag, 16, 8)
728#define PCI_CFG_GET_DEVNO(tag)                  PCI__EXT(tag, 11, 5)
729#define PCI_CFG_GET_FUNCNO(tag)                 PCI__EXT(tag,  8, 3)
730#define PCI_CFG_GET_REGNO(tag)                  PCI__EXT(tag,  0, 8)
731
732/*
733 * Table 306: PCI Configuration Data
734 *
735 * 31:00 ConfigData     The data is transferred to/from the PCI bus when
736 *                      the CPU accesses this register and the ConfigEn
737 *                      bit in the Configuration Address register is set
738 *
739 * A CPU access to this register causes the GT64260 to perform a Configuration
740 * or Special cycle on the PCI bus.
741 */
742
743
744/*
745 * Table 307: PCI Interrupt Acknowledge (This register is READ ONLY)
746 * 31:00 IntAck         A CPU read access to this register forces an
747 *                      interrupt acknowledge cycle on the PCI bus.
748 */
749
750
751/*
752 * Table 308: PCI SERR* Mask
753 *
754 * NOTE: The GT64260 asserts SERR* only if SERR* is enabled via the PCI Status
755 *       and Command register.
756 * If the corresponding bit is set, then asserts SERR* upon ...
757 */
758#define PCI_SERRMSK_SAPerr      PCI__BIT(0)     /* PCI slave detection of bad
759                                                 * address parity. */
760#define PCI_SERRMSK_SWrPerr     PCI__BIT(1)     /* PCI slave detection of bad
761                                                 * write data parity. */
762#define PCI_SERRMSK_SRdPerr     PCI__BIT(2)     /* a PERR* response to read
763                                                 * data driven by the PCI
764                                                 * slave. */
765#define PCI_SERRMSK_MAPerr      PCI__BIT(4)     /* a PERR* response to an
766                                                 * address driven by the PCI
767                                                 * master. */
768#define PCI_SERRMSK_MWrPerr     PCI__BIT(5)     /* a PERR* response to write
769                                                 * data driven by the PCI
770                                                 * master. */
771#define PCI_SERRMSK_MRdPerr     PCI__BIT(6)     /* bad data parity detection
772                                                 * during a PCI master read
773                                                 * transaction. */
774#define PCI_SERRMSK_MMabort     PCI__BIT(8)     /* a PCI master generation of
775                                                 * master abort. */
776#define PCI_SERRMSK_MTabort     PCI__BIT(9)     /* a PCI master detection of
777                                                 * target abort. */
778#define PCI_SERRMSK_MRetry      PCI__BIT(11)    /* a PCI master reaching retry
779                                                 * counter limit. */
780#define PCI_SERRMSK_SMabort     PCI__BIT(16)    /* a PCI slave detection of
781                                                 * master abort. */
782#define PCI_SERRMSK_STabort     PCI__BIT(17)    /* a PCI slave termination of
783                                                 * a transaction with Target
784                                                 * Abort. */
785#define PCI_SERRMSK_SAccProt    PCI__BIT(18)    /* a PCI slave access protect
786                                                 * violation. */
787#define PCI_SERRMSK_SWrProt     PCI__BIT(19)    /* a PCI slave write protect
788                                                 * violation. */
789#define PCI_SERRMSK_SRdBuf      PCI__BIT(20)    /* the PCI slave's read buffer,
790                                                 * discard timer expires */
791#define PCI_SERRMSK_Arb         PCI__BIT(21)    /* the internal PCI arbiter
792                                                 * detection of a broken PCI
793                                                 * master. */
794
795#define PCI_SERRMSK_ALL_ERRS \
796        (PCI_SERRMSK_SAPerr|PCI_SERRMSK_SWrPerr|PCI_SERRMSK_SRdPerr \
797        |PCI_SERRMSK_MAPerr|PCI_SERRMSK_MWrPerr|PCI_SERRMSK_MRdPerr \
798        |PCI_SERRMSK_MMabort|PCI_SERRMSK_MTabort|PCI_SERRMSK_MRetry \
799        |PCI_SERRMSK_SMabort|PCI_SERRMSK_STabort|PCI_SERRMSK_SAccProt \
800        |PCI_SERRMSK_SWrProt|PCI_SERRMSK_SRdBuf|PCI_SERRMSK_Arb)
801
802
803
804/*
805 * Table 309: PCI Error Address (Low) -- Read Only.
806 * 31:00 ErrAddr        PCI address bits [31:0] are latched upon an error
807 *                      condition.  Upon address latch, no new addresses can
808 *                      be registered (due to additional error condition) until
809 *                      the register is being read.
810 */
811
812
813
814/*
815 * Table 310: PCI Error Address (High)  Applicable only when running DAC cycles.
816 * 31:00 ErrAddr        PCI address bits [63:32] are latched upon
817 *                      error condition.
818 *
819 * NOTE: Upon data sample, no new data is latched until the PCI Error Low
820 *       Address register is read. This means that PCI Error Low Address
821 *       register must bethe last register read by the interrupt handler.
822 */
823
824/*
825 * Table 311: PCI Error Data (Low)
826 * 31:00 ErrData        PCI data bits [31:00] are latched upon error condition.
827 */
828
829/*
830 * Table 312: PCI Error Data (High)     Applicable only when running
831 *                                      64-bit cycles.
832 * 31:00 ErrData        PCI data bits [63:32] are latched upon error condition.
833 */
834
835/*
836 * Table 313: PCI Error Command
837 * 03:00 ErrCmd         PCI command is latched upon error condition.
838 * 07:04 Reserved
839 * 15:08 ErrBE          PCI byte enable is latched upon error condition.
840 * 16:16 ErrPAR         PCI PAR is latched upon error condition.
841 * 17:17 ErrPAR64       PCI PAR64 is latched upon error condition.
842 *                      Applicable only when running 64-bit cycles.
843 * 31:18 Reserved
844 * NOTE: Upon data sample, no new data is latched until the PCI Error Low
845 * Address register is read. This means that PCI Error Low Address register
846 * must be the last register read by the interrupt handler.
847 */
848#define PCI_ERRCMD_Cmd_GET(v)           PCI__EXT(v, 0, 4)
849#define PCI_ERRCMD_ByteEn_GET(v)        PCI__EXT(v, 8, 8)
850#define PCI_ERRCMD_PAR                  PCI__BIT(16)
851#define PCI_ERRCMD_PAR64                PCI__BIT(17)
852
853/*
854 * Table 314: PCI Interrupt Cause
855 * 1. All bits are Clear Only. A cause bit set upon error event occurrence.
856 *    A write of 0 clears the bit. A write of 1 has no affect.
857 * 2. PCI Interrupt bits are organized in four groups:
858 *    bits[ 7: 0] for address and data parity errors,
859 *    bits[15: 8] for PCI master transaction failure (possible external
860 *                target problem),
861 *    bits[23:16] for slave response failure (possible external master problem),
862 *    bits[26:24] for external PCI events that require CPU handle.
863 */
864#define PCI_IC_SAPerr           PCI__BIT(0)     /* The PCI slave detected
865                                                 * bad address parity. */
866#define PCI_IC_SWrPerr          PCI__BIT(1)     /* The PCI slave detected
867                                                 * bad write data parity. */
868#define PCI_IC_SRdPerr          PCI__BIT(2)     /* PERR* response to read
869                                                 * data driven by PCI slave. */
870#define PCI_IC_MAPerr           PCI__BIT(4)     /* PERR* response to address
871                                                 * driven by the PCI master. */
872#define PCI_IC_MWrPerr          PCI__BIT(5)     /* PERR* response to write data
873                                                 * driven by the PCI master. */
874#define PCI_IC_MRdPerr          PCI__BIT(6)     /* Bad data parity detected
875                                                 * during the PCI master read
876                                                 * transaction. */
877#define PCI_IC_MMabort          PCI__BIT(8)     /* The PCI master generated
878                                                 * master abort. */
879#define PCI_IC_MTabort          PCI__BIT(9)     /* The PCI master detected
880                                                 * target abort. */
881#define PCI_IC_MMasterEn        PCI__BIT(10)    /* An attempt to generate a PCI
882                                                 * transaction while master is
883                                                 * not enabled. */
884#define PCI_IC_MRetry           PCI__BIT(11)    /* The PCI master reached
885                                                 * retry counter limit. */
886#define PCI_IC_SMabort          PCI__BIT(16)    /* The PCI slave detects an il-
887                                                 * legal master termination. */
888#define PCI_IC_STabort          PCI__BIT(17)    /* The PCI slave terminates a
889                                                 * transaction with Target
890                                                 * Abort. */
891#define PCI_IC_SAccProt         PCI__BIT(18)    /* A PCI slave access protect
892                                                 * violation. */
893#define PCI_IC_SWrProt          PCI__BIT(19)    /* A PCI slave write protect
894                                                 * violation. */
895#define PCI_IC_SRdBuf           PCI__BIT(20)    /* A PCI slave read buffer
896                                                 * discard timer expired. */
897#define PCI_IC_Arb              PCI__BIT(21)    /* Internal PCI arbiter detec-
898                                                 * tion of a broken master. */
899#define PCI_IC_BIST             PCI__BIT(24)    /* PCI BIST Interrupt */
900#define PCI_IC_PMG              PCI__BIT(25)    /* PCI Power Management
901                                                 * Interrupt */
902#define PCI_IC_PRST             PCI__BIT(26)    /* PCI Reset Assert */
903
904/*
90531:27 Sel Specifies the error event currently being reported in the
906Error Address, Error Data, and Error Command registers.
907*/
908#define PCI_IC_SEL_GET(v)       PCI__EXT((v), 27, 5)
909#define PCI_IC_SEL_SAPerr       0x00
910#define PCI_IC_SEL_SWrPerr      0x01
911#define PCI_IC_SEL_SRdPerr      0x02
912#define PCI_IC_SEL_MAPerr       0x04
913#define PCI_IC_SEL_MWrPerr      0x05
914#define PCI_IC_SEL_MRdPerr      0x06
915#define PCI_IC_SEL_MMabort      0x08
916#define PCI_IC_SEL_MTabort      0x09
917#define PCI_IC_SEL_MMasterEn    0x0a
918#define PCI_IC_SEL_MRetry       0x0b
919#define PCI_IC_SEL_SMabort      0x10
920#define PCI_IC_SEL_STabort      0x11
921#define PCI_IC_SEL_SAccProt     0x12
922#define PCI_IC_SEL_SWrProt      0x13
923#define PCI_IC_SEL_SRdBuf       0x14
924#define PCI_IC_SEL_Arb          0x15
925#define PCI_IC_SEL_BIST         0x18
926#define PCI_IC_SEL_PMG          0x19
927#define PCI_IC_SEL_PRST         0x1a
928
929#define PCI_IC_SEL_Strings { \
930        "SAPerr",  "SWrPerr", "SRdPerr",   "Rsvd#03", \
931        "MAPerr",  "MWrPerr", "MRdPerr",   "Rsvd#07", \
932        "MMabort", "MTabort", "MMasterEn", "MRetry", \
933        "Rsvd#0c", "Rsvd#0d", "Rsvd#0e",   "Rsvd#0f", \
934        "SMabort", "STabort", "SAccProt",  "SWrProt", \
935        "SRdBuf",  "Arb",     "Rsvd#16",   "Rsvd#17", \
936        "BIST",    "PMG",     "PRST",      "Rsvd#1b", \
937        "Rsvd#1c", "Rsvd#1d", "Rsvd#1e",   "Rsvd#1f" }
938
939/*
940 * Table 315: PCI Error Mask
941 * If the corresponding bit is 1, that interrupt is enabled
942 * Bits 3, 7, 12:15, 22:23, 27:31 are reserved.
943 */
944#define PCI_ERRMASK_SAPErr              PCI__BIT(0)
945#define PCI_ERRMASK_SWrPErr             PCI__BIT(1)
946#define PCI_ERRMASK_SRdPErr             PCI__BIT(2)
947#define PCI_ERRMASK_MAPErr              PCI__BIT(4)
948#define PCI_ERRMASK_MWRPErr             PCI__BIT(5)
949#define PCI_ERRMASK_MRDPErr             PCI__BIT(6)
950#define PCI_ERRMASK_MMAbort             PCI__BIT(8)
951#define PCI_ERRMASK_MTAbort             PCI__BIT(9)
952#define PCI_ERRMASK_MMasterEn           PCI__BIT(10)
953#define PCI_ERRMASK_MRetry              PCI__BIT(11)
954#define PCI_ERRMASK_SMAbort             PCI__BIT(16)
955#define PCI_ERRMASK_STAbort             PCI__BIT(17)
956#define PCI_ERRMASK_SAccProt            PCI__BIT(18)
957#define PCI_ERRMASK_SWrProt             PCI__BIT(19)
958#define PCI_ERRMASK_SRdBuf              PCI__BIT(20)
959#define PCI_ERRMASK_Arb                 PCI__BIT(21)
960#define PCI_ERRMASK_BIST                PCI__BIT(24)
961#define PCI_ERRMASK_PMG                 PCI__BIT(25)
962#define PCI_ERRMASK_PRST                PCI__BIT(26)
963
964#endif /* _DEV_GTPCIREG_H_ */
Note: See TracBrowser for help on using the repository browser.