source: rtems/c/src/lib/libbsp/powerpc/beatnik/include/bsp.h @ fe484280

4.104.11
Last change on this file since fe484280 was fe484280, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 8, 2009 at 9:18:38 PM

2009-12-08 Joel Sherrill <joel.sherrill@…>

  • include/bsp.h: BSP should not define CONFIGURE_NUMBER_OF_TERMIOS_PORTS.
  • Property mode set to 100644
File size: 7.6 KB
Line 
1/*
2 *  bsp.h  -- contain BSP API definition.
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
11 *
12 *  Modified for the 'beatnik' BSP by T. Straumann, 2005-2007.
13 *
14 * bsp.h,v 1.9.4.2 2003/09/04 18:45:20 joel Exp
15 */
16#ifndef LIBBSP_BEATNIK_BSP_H
17#define LIBBSP_BEATNIK_BSP_H
18
19#include <bspopts.h>
20
21#include <rtems.h>
22#include <rtems/console.h>
23#include <libcpu/io.h>
24#include <rtems/clockdrv.h>
25#include <bsp/vectors.h>
26
27#ifdef __cplusplus
28  extern "C" {
29#endif
30
31/* Board type */
32typedef enum {
33        Unknown = 0,
34        MVME5500,
35        MVME6100
36} BSP_BoardType;
37
38BSP_BoardType
39BSP_getBoardType();
40
41/* Discovery Version */
42
43typedef enum {
44        unknown    = 0,
45        GT_64260_A,             /* Revision 0x10 */
46        GT_64260_B,         /* Revision 0x20 */
47        MV_64360,
48} DiscoveryVersion;
49
50/* Determine the type of discovery chip on this board; info
51 * is cached and repeated calls just return the cached value.
52 *
53 * If a non-zero argument is passed, the routine panics
54 * (BSP_panic) if no recognized bridge is found;
55 */
56 
57DiscoveryVersion
58BSP_getDiscoveryVersion(int assertion);
59
60/*
61 *  confdefs.h overrides for this BSP:
62 *   - Interrupt stack space is not minimum if defined.
63 */
64#define BSP_INTERRUPT_STACK_SIZE          (16 * 1024)
65
66/*
67 *  base address definitions for several devices
68 */
69#define BSP_MV64x60_BASE                (0xf1000000)
70#define BSP_MV64x60_DEV1_BASE           (0xf1100000)
71#define BSP_UART_IOBASE_COM1            ((BSP_MV64x60_DEV1_BASE)+0x20000)
72#define BSP_UART_IOBASE_COM2            ((BSP_MV64x60_DEV1_BASE)+0x21000)
73#define BSP_UART_USE_SHARED_IRQS
74
75#define BSP_NVRAM_BASE_ADDR                     (0xf1110000)
76#define BSP_NVRAM_END_ADDR                      (0xf1117fff)
77#define BSP_NVRAM_RTC_START                     (0xf1117ff8)
78
79#define BSP_NVRAM_BOOTPARMS_START       (0xf1111000)
80#define BSP_NVRAM_BOOTPARMS_END         (0xf1111fff)
81
82
83/* This is only active/used during early init. It defines
84 * the hose0 base for the shared/generic pci code.
85 * Our own BSP specific pci initialization will then
86 * override the PCI configuration (see gt_pci_init.c:BSP_pci_initialize)
87 */
88
89#define PCI_CONFIG_ADDR                         (BSP_MV64x60_BASE + 0xcf8)
90#define PCI_CONFIG_DATA                         (BSP_MV64x60_BASE + 0xcfc)
91
92/* our wonderful PCI initialization remaps everything to CPU addresses
93 * - before calling BSP_pci_initialize() this is NOT VALID, however
94 * and the deprecated inl()/outl() etc won't work!
95 */
96#define _IO_BASE                                        0x00000000
97/* wonderful MotLoad has the base address as seen from the CPU programmed into config space :-) */
98#define PCI_MEM_BASE                            0
99#define PCI_MEM_BASE_ADJUSTMENT         0
100#define PCI_DRAM_OFFSET                         0
101
102/* PCI <-> local address mapping - no sophisticated windows
103 * (i.e., no support for cached regions etc. you read a BAR
104 * from config space and that's 1:1 where the CPU sees it).
105 * Our memory is mapped 1:1 to PCI also.
106 */
107#define BSP_PCI2LOCAL_ADDR(a) ((uint32_t)(a))
108#define BSP_LOCAL2PCI_ADDR(a) ((uint32_t)(a))
109
110#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS  32
111
112#define BSP_CONSOLE_PORT                        BSP_UART_COM1
113#define BSP_UART_BAUD_BASE                      115200
114
115/* I2C Devices */
116/* Note that the i2c addresses stated in the manual are
117 * left-shifted by one bit.
118 */
119#define BSP_VPD_I2C_ADDR                        (0xA8>>1)               /* the VPD EEPROM  */
120#define BSP_USR_I2C_ADDR                        (0xAA>>1)               /* the user EEPROM */
121#define BSP_THM_I2C_ADDR                        (0x90>>1)               /* the DS1621 temperature sensor & thermostat */
122
123#define BSP_I2C_BUS_DESCRIPTOR          gt64260_i2c_bus_descriptor
124
125#define BSP_I2C_BUS0_NAME             "/dev/i2c0"
126
127#define BSP_I2C_VPD_EEPROM_NAME       "vpd-eeprom"
128#define BSP_I2C_USR_EEPROM_NAME       "usr-eeprom"
129#define BSP_I2C_DS1621_NAME           "ds1621"
130#define BSP_I2C_THM_NAME              BSP_I2C_DS1621_NAME
131#define BSP_I2C_DS1621_RAW_NAME       "ds1621-raw"
132
133#define BSP_I2C_VPD_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME)
134#define BSP_I2C_USR_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME)
135#define BSP_I2C_DS1621_DEV_NAME          (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME)
136#define BSP_I2C_THM_DEV_NAME              BSP_I2C_DS1621_DEV_NAME
137#define BSP_I2C_DS1621_RAW_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME)
138
139
140/* Initialize the I2C driver and register all devices
141 * RETURNS 0 on success, -1 on error.
142 *
143 * Access to the VPD and user EEPROMS as well
144 * as the ds1621 temperature sensor is possible
145 * by means of file nodes
146 *
147 *   /dev/i2c0.vpd-eeprom   (read-only)
148 *   /dev/i2c0.usr-eeprom   (read-write)
149 *   /dev/i2c0.ds1621       (read-only; one byte: board-temp in degC)
150 *   /dev/i2c0.ds1621-raw   (read-write; transfer bytes to/from the ds1621)
151 */
152int
153BSP_i2c_initialize();
154
155/* Networking; */
156#include <bsp/bsp_bsdnet_attach.h>
157
158/* NOT FOR PUBLIC USE BELOW HERE */
159#define BSP_PCI_HOSE0_MEM_BASE          0x80000000      /* must be aligned to size */
160#define BSP_PCI_HOSE0_MEM_SIZE          0x20000000
161
162#define BSP_PCI_HOSE1_MEM_BASE          0xe0000000
163
164#define BSP_DEV_AND_PCI_IO_BASE         0xf0000000
165#define BSP_DEV_AND_PCI_IO_SIZE         0x10000000
166
167/* maintain coherency between CPU and GT64340 ethernet (& possibly other discovery components) */
168#define BSP_RW_PAGE_ATTRIBUTES  TRIV121_ATTR_M
169
170extern unsigned BSP_pci_hose1_bus_base;
171
172void BSP_pci_initialize();
173
174/* Exception Handling */
175
176/* Use a task notepad to attach user exception handler info;
177 * may be changed by application startup code (EPICS uses 11)
178 */
179#define BSP_EXCEPTION_NOTEPAD           14
180 
181#ifndef ASM
182
183#define outport_byte(port,value) outb(value,port)
184#define outport_word(port,value) outw(value,port)
185#define outport_long(port,value) outl(value,port)
186
187#define inport_byte(port,value) (value = inb(port))
188#define inport_word(port,value) (value = inw(port))
189#define inport_long(port,value) (value = inl(port))
190/*
191 * Vital Board data Start using DATA RESIDUAL
192 */
193/*
194 * Total memory using RESIDUAL DATA
195 */
196extern unsigned int BSP_mem_size;
197/*
198 * Start of the heap
199 */
200extern unsigned int BSP_heap_start;
201/*
202 * PCI Bus Frequency
203 */
204extern unsigned int BSP_bus_frequency;
205/*
206 * processor clock frequency
207 */
208extern unsigned int BSP_processor_frequency;
209/*
210 * Time base divisior (how many tick for 1 second).
211 */
212extern unsigned int BSP_time_base_divisor;
213
214extern char BSP_productIdent[20];
215extern char BSP_serialNumber[20];
216
217extern char BSP_enetAddr0[7];
218extern char BSP_enetAddr1[7];
219
220/*
221 * The commandline as passed from the bootloader.
222 */
223extern char *BSP_commandline_string;
224
225
226#define BSP_Convert_decrementer( _value ) \
227  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
228
229extern rtems_configuration_table  BSP_Configuration;
230extern void BSP_panic(char *s);
231extern void bsp_reset(void);
232extern int BSP_disconnect_clock_handler (void);
233extern int BSP_connect_clock_handler (void);
234
235/* clear hostbridge errors
236 *
237 * enableMCP: whether to enable MCP checkstop / machine check interrupts
238 *            on the hostbridge and in HID0.
239 *
240 *            NOTE: The 5500 and 6100 boards have NO PHYSICAL CONNECTION
241 *                  to MCP so 'enableMCP' will always fail!
242 *
243 * quiet    : be silent
244 *
245 * RETURNS  : PCI status (hose 0 in byte 0, host 1 in byte 1) and
246 *            VME bridge status (upper 16 bits).
247 *            Zero if no errors were found.
248 */
249extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
250
251/* clear vme bridge errors and return (bridge-dependent) 16-bit status
252 *
253 * quiet    : be silent
254 *
255 * RETURNS  : 0 if there were no errors, non-zero, bridge-dependent
256 *            16-bit error status on error.
257 *
258 */
259extern unsigned short
260(*_BSP_clear_vmebridge_errors)(int);
261
262
263#endif
264
265#ifdef __cplusplus
266  }
267#endif
268
269#endif
Note: See TracBrowser for help on using the repository browser.