source: rtems/c/src/lib/libbsp/powerpc/beatnik/include/bsp.h @ 64a31017

4.10
Last change on this file since 64a31017 was 64a31017, checked in by Till Straumann <strauman@…>, on 05/16/11 at 15:12:31

2011-05-16 Till Straumann <strauman@…>

  • include/bsp.h: define CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK
  • Property mode set to 100644
File size: 7.7 KB
Line 
1/*
2 *  bsp.h  -- contain BSP API definition.
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
11 *
12 *  Modified for the 'beatnik' BSP by T. Straumann, 2005-2007.
13 *
14 * bsp.h,v 1.9.4.2 2003/09/04 18:45:20 joel Exp
15 */
16#ifndef LIBBSP_BEATNIK_BSP_H
17#define LIBBSP_BEATNIK_BSP_H
18
19#include <bspopts.h>
20
21#include <rtems.h>
22#include <rtems/console.h>
23#include <libcpu/io.h>
24#include <rtems/clockdrv.h>
25#include <bsp/vectors.h>
26
27#ifdef __cplusplus
28  extern "C" {
29#endif
30
31/* Board type */
32typedef enum {
33        Unknown = 0,
34        MVME5500,
35        MVME6100
36} BSP_BoardType;
37
38BSP_BoardType
39BSP_getBoardType();
40
41/* Discovery Version */
42
43typedef enum {
44        unknown    = 0,
45        GT_64260_A,             /* Revision 0x10 */
46        GT_64260_B,         /* Revision 0x20 */
47        MV_64360,
48} DiscoveryVersion;
49
50/* Determine the type of discovery chip on this board; info
51 * is cached and repeated calls just return the cached value.
52 *
53 * If a non-zero argument is passed, the routine panics
54 * (BSP_panic) if no recognized bridge is found;
55 */
56 
57DiscoveryVersion
58BSP_getDiscoveryVersion(int assertion);
59
60/*
61 *  confdefs.h overrides for this BSP:
62 *   - Interrupt stack space is not minimum if defined.
63 */
64#define BSP_INTERRUPT_STACK_SIZE          (16 * 1024)
65
66#define CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK
67
68/*
69 *  base address definitions for several devices
70 */
71#define BSP_MV64x60_BASE                (0xf1000000)
72#define BSP_MV64x60_DEV1_BASE           (0xf1100000)
73#define BSP_UART_IOBASE_COM1            ((BSP_MV64x60_DEV1_BASE)+0x20000)
74#define BSP_UART_IOBASE_COM2            ((BSP_MV64x60_DEV1_BASE)+0x21000)
75#define BSP_UART_USE_SHARED_IRQS
76
77#define BSP_NVRAM_BASE_ADDR                     (0xf1110000)
78#define BSP_NVRAM_END_ADDR                      (0xf1117fff)
79#define BSP_NVRAM_RTC_START                     (0xf1117ff8)
80
81#define BSP_NVRAM_BOOTPARMS_START       (0xf1111000)
82#define BSP_NVRAM_BOOTPARMS_END         (0xf1111fff)
83
84
85/* This is only active/used during early init. It defines
86 * the hose0 base for the shared/generic pci code.
87 * Our own BSP specific pci initialization will then
88 * override the PCI configuration (see gt_pci_init.c:BSP_pci_initialize)
89 */
90
91#define PCI_CONFIG_ADDR                         (BSP_MV64x60_BASE + 0xcf8)
92#define PCI_CONFIG_DATA                         (BSP_MV64x60_BASE + 0xcfc)
93
94/* our wonderful PCI initialization remaps everything to CPU addresses
95 * - before calling BSP_pci_initialize() this is NOT VALID, however
96 * and the deprecated inl()/outl() etc won't work!
97 */
98#define _IO_BASE                                        0x00000000
99/* wonderful MotLoad has the base address as seen from the CPU programmed into config space :-) */
100#define PCI_MEM_BASE                            0
101#define PCI_MEM_BASE_ADJUSTMENT         0
102#define PCI_DRAM_OFFSET                         0
103
104/* PCI <-> local address mapping - no sophisticated windows
105 * (i.e., no support for cached regions etc. you read a BAR
106 * from config space and that's 1:1 where the CPU sees it).
107 * Our memory is mapped 1:1 to PCI also.
108 */
109#define BSP_PCI2LOCAL_ADDR(a) ((uint32_t)(a))
110#define BSP_LOCAL2PCI_ADDR(a) ((uint32_t)(a))
111
112#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS  32
113
114#define BSP_CONSOLE_PORT                        BSP_UART_COM1
115#define BSP_UART_BAUD_BASE                      115200
116
117/* I2C Devices */
118/* Note that the i2c addresses stated in the manual are
119 * left-shifted by one bit.
120 */
121#define BSP_VPD_I2C_ADDR                        (0xA8>>1)               /* the VPD EEPROM  */
122#define BSP_USR_I2C_ADDR                        (0xAA>>1)               /* the user EEPROM */
123#define BSP_THM_I2C_ADDR                        (0x90>>1)               /* the DS1621 temperature sensor & thermostat */
124
125#define BSP_I2C_BUS_DESCRIPTOR          gt64260_i2c_bus_descriptor
126
127#define BSP_I2C_BUS0_NAME             "/dev/i2c0"
128
129#define BSP_I2C_VPD_EEPROM_NAME       "vpd-eeprom"
130#define BSP_I2C_USR_EEPROM_NAME       "usr-eeprom"
131#define BSP_I2C_DS1621_NAME           "ds1621"
132#define BSP_I2C_THM_NAME              BSP_I2C_DS1621_NAME
133#define BSP_I2C_DS1621_RAW_NAME       "ds1621-raw"
134
135#define BSP_I2C_VPD_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME)
136#define BSP_I2C_USR_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME)
137#define BSP_I2C_DS1621_DEV_NAME          (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME)
138#define BSP_I2C_THM_DEV_NAME              BSP_I2C_DS1621_DEV_NAME
139#define BSP_I2C_DS1621_RAW_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME)
140
141
142/* Initialize the I2C driver and register all devices
143 * RETURNS 0 on success, -1 on error.
144 *
145 * Access to the VPD and user EEPROMS as well
146 * as the ds1621 temperature sensor is possible
147 * by means of file nodes
148 *
149 *   /dev/i2c0.vpd-eeprom   (read-only)
150 *   /dev/i2c0.usr-eeprom   (read-write)
151 *   /dev/i2c0.ds1621       (read-only; one byte: board-temp in degC)
152 *   /dev/i2c0.ds1621-raw   (read-write; transfer bytes to/from the ds1621)
153 */
154int
155BSP_i2c_initialize();
156
157/* Networking; */
158#if defined(RTEMS_NETWORKING)
159#include <bsp/bsp_bsdnet_attach.h>
160#endif
161
162/* NOT FOR PUBLIC USE BELOW HERE */
163#define BSP_PCI_HOSE0_MEM_BASE          0x80000000      /* must be aligned to size */
164#define BSP_PCI_HOSE0_MEM_SIZE          0x20000000
165
166#define BSP_PCI_HOSE1_MEM_BASE          0xe0000000
167
168#define BSP_DEV_AND_PCI_IO_BASE         0xf0000000
169#define BSP_DEV_AND_PCI_IO_SIZE         0x10000000
170
171/* maintain coherency between CPU and GT64340 ethernet (& possibly other discovery components) */
172#define BSP_RW_PAGE_ATTRIBUTES  TRIV121_ATTR_M
173
174extern unsigned BSP_pci_hose1_bus_base;
175
176void BSP_pci_initialize();
177
178/* Exception Handling */
179
180/* Use a task notepad to attach user exception handler info;
181 * may be changed by application startup code (EPICS uses 11)
182 */
183#define BSP_EXCEPTION_NOTEPAD           14
184 
185#ifndef ASM
186
187#define outport_byte(port,value) outb(value,port)
188#define outport_word(port,value) outw(value,port)
189#define outport_long(port,value) outl(value,port)
190
191#define inport_byte(port,value) (value = inb(port))
192#define inport_word(port,value) (value = inw(port))
193#define inport_long(port,value) (value = inl(port))
194/*
195 * Vital Board data Start using DATA RESIDUAL
196 */
197/*
198 * Total memory using RESIDUAL DATA
199 */
200extern unsigned int BSP_mem_size;
201/*
202 * Start of the heap
203 */
204extern unsigned int BSP_heap_start;
205/*
206 * PCI Bus Frequency
207 */
208extern unsigned int BSP_bus_frequency;
209/*
210 * processor clock frequency
211 */
212extern unsigned int BSP_processor_frequency;
213/*
214 * Time base divisior (how many tick for 1 second).
215 */
216extern unsigned int BSP_time_base_divisor;
217
218extern char BSP_productIdent[20];
219extern char BSP_serialNumber[20];
220
221extern char BSP_enetAddr0[7];
222extern char BSP_enetAddr1[7];
223
224/*
225 * The commandline as passed from the bootloader.
226 */
227extern char *BSP_commandline_string;
228
229
230#define BSP_Convert_decrementer( _value ) \
231  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
232
233extern rtems_configuration_table  BSP_Configuration;
234extern void BSP_panic(char *s);
235extern void bsp_reset(void);
236extern int BSP_disconnect_clock_handler (void);
237extern int BSP_connect_clock_handler (void);
238
239/* clear hostbridge errors
240 *
241 * enableMCP: whether to enable MCP checkstop / machine check interrupts
242 *            on the hostbridge and in HID0.
243 *
244 *            NOTE: The 5500 and 6100 boards have NO PHYSICAL CONNECTION
245 *                  to MCP so 'enableMCP' will always fail!
246 *
247 * quiet    : be silent
248 *
249 * RETURNS  : PCI status (hose 0 in byte 0, host 1 in byte 1) and
250 *            VME bridge status (upper 16 bits).
251 *            Zero if no errors were found.
252 */
253extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
254
255/* clear vme bridge errors and return (bridge-dependent) 16-bit status
256 *
257 * quiet    : be silent
258 *
259 * RETURNS  : 0 if there were no errors, non-zero, bridge-dependent
260 *            16-bit error status on error.
261 *
262 */
263extern unsigned short
264(*_BSP_clear_vmebridge_errors)(int);
265
266
267#endif
268
269#ifdef __cplusplus
270  }
271#endif
272
273#endif
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