1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup or1ksim_uart |
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5 | * |
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6 | * @brief UART support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/license/LICENSE |
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15 | */ |
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16 | |
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17 | #include <libchip/sersupp.h> |
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18 | #include <bsp/or1ksim.h> |
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19 | #include <bsp.h> |
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20 | #include <bsp/irq.h> |
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21 | #include <bsp/uart.h> |
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22 | #include <rtems/score/isr.h> |
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23 | |
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24 | static void uart_initialize(int minor); |
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25 | static int uart_first_open(int major, int minor, void *arg); |
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26 | static int uart_last_close(int major, int minor, void *arg); |
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27 | static int uart_read_polled(int minor); |
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28 | static ssize_t uart_write(int minor, const char *buf, size_t len); |
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29 | static void uart_write_polled(int minor, char c); |
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30 | static int uart_set_attributes(int minor, const struct termios *t); |
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31 | |
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32 | #if 0 |
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33 | /* |
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34 | * These will be useful when the driver supports interrupt driven IO. |
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35 | */ |
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36 | static rtems_vector_number uart_get_irq_number(const console_tbl *ct) |
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37 | { |
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38 | return ct->ulIntVector; |
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39 | } |
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40 | |
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41 | static uint32_t uart_get_baud(const console_tbl *ct) |
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42 | { |
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43 | return ct->ulClock; |
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44 | } |
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45 | #endif |
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46 | |
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47 | static void uart_set_baud(int baud) |
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48 | { |
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49 | int divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud); |
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50 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) |= |
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51 | OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB; |
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52 | |
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53 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW) = divisor & 0xff; |
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54 | |
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55 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH) = |
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56 | (divisor >> 8) & 0xff; |
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57 | |
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58 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) &= |
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59 | ~(OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB); |
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60 | } |
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61 | |
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62 | static void uart_initialize(int minor) |
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63 | { |
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64 | /* Disable all interrupts */ |
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65 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00; |
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66 | |
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67 | /* Reset receiver and transmitter */ |
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68 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_FIFO_CTRL) = |
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69 | OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO | |
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70 | OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR | |
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71 | OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT | |
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72 | OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14; |
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73 | |
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74 | /* Set data pattern configuration */ |
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75 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) = |
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76 | OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 & |
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77 | (OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP | |
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78 | OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY); |
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79 | |
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80 | /* Set baud rate */ |
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81 | uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD); |
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82 | } |
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83 | |
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84 | static int uart_first_open(int major, int minor, void *arg) |
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85 | { |
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86 | rtems_libio_open_close_args_t *oc = (rtems_libio_open_close_args_t *) arg; |
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87 | struct rtems_termios_tty *tty = (struct rtems_termios_tty *) oc->iop->data1; |
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88 | const console_tbl *ct = Console_Port_Tbl [minor]; |
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89 | console_data *cd = &Console_Port_Data [minor]; |
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90 | |
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91 | cd->termios_data = tty; |
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92 | rtems_termios_set_initial_baud(tty, ct->ulClock); |
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93 | |
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94 | return 0; |
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95 | } |
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96 | |
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97 | static int uart_last_close(int major, int minor, void *arg) |
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98 | { |
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99 | return 0; |
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100 | } |
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101 | |
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102 | static int uart_read_polled(int minor) |
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103 | { |
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104 | unsigned char lsr; |
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105 | |
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106 | /* Get a character when avaiable */ |
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107 | do { |
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108 | lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); |
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109 | } while ((lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_DR) |
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110 | != OR1KSIM_BSP_UART_REG_LINE_STATUS_DR); |
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111 | |
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112 | return OR1KSIM_REG(OR1KSIM_BSP_UART_REG_RX); |
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113 | } |
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114 | |
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115 | static void uart_write_polled(int minor, char c) |
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116 | { |
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117 | unsigned char lsr; |
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118 | const uint32_t transmit_finished = |
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119 | (OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT | |
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120 | OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE); |
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121 | |
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122 | /* Wait until there is no pending data in the transmitter FIFO (empty) */ |
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123 | do { |
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124 | lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); |
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125 | } while (!(lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE)); |
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126 | |
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127 | OR1KSIM_REG(OR1KSIM_BSP_UART_REG_TX) = c; |
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128 | |
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129 | /* Wait until trasmit data is finished */ |
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130 | do { |
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131 | lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); |
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132 | } while ( (lsr & transmit_finished) != transmit_finished ); |
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133 | } |
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134 | |
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135 | static ssize_t uart_write( |
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136 | int minor, |
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137 | const char *s, |
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138 | size_t n |
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139 | ) |
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140 | { |
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141 | ssize_t i = 0; |
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142 | |
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143 | for (i = 0; i < n; ++i){ |
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144 | uart_write_polled(minor, s [i]); |
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145 | } |
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146 | |
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147 | return n; |
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148 | } |
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149 | |
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150 | static int uart_set_attributes(int minor, const struct termios *term) |
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151 | { |
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152 | return -1; |
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153 | } |
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154 | |
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155 | const console_fns or1ksim_uart_fns = { |
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156 | .deviceProbe = libchip_serial_default_probe, |
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157 | .deviceFirstOpen = uart_first_open, |
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158 | .deviceLastClose = uart_last_close, |
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159 | .deviceRead = uart_read_polled, |
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160 | .deviceWrite = uart_write, |
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161 | .deviceInitialize = uart_initialize, |
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162 | .deviceWritePolled = uart_write_polled, |
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163 | .deviceSetAttributes = uart_set_attributes, |
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164 | .deviceOutputUsesInterrupts = false |
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165 | }; |
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