source: rtems/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c @ f3b29236

Last change on this file since f3b29236 was f3b29236, checked in by Sebastian Huber <sebastian.huber@…>, on Sep 18, 2017 at 6:22:38 AM

bsps: Clock_driver_support_install_isr()

Remove old ISR parameter since is not used by the clock driver shell.
Make an implementation optional.

Update #3139.

  • Property mode set to 100644
File size: 4.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup bsp_clock
5 *
6 * @brief or1k clock support.
7 */
8
9/*
10 * generic_or1k Clock driver
11 *
12 * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
13 *
14 * The license and distribution terms for this file may be
15 * found in the file LICENSE in this distribution or at
16 * http://www.rtems.org/license/LICENSE
17 */
18
19#include <rtems.h>
20#include <bsp.h>
21#include <bsp/irq.h>
22#include <bsp/generic_or1k.h>
23#include <rtems/score/cpu.h>
24#include <rtems/score/or1k-utility.h>
25#include <rtems/timecounter.h>
26
27/* The number of clock cycles before generating a tick timer interrupt. */
28#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT     0x09ED9
29#define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS     10
30
31static struct timecounter or1ksim_tc;
32
33/* CPU counter */
34static CPU_Counter_ticks cpu_counter_ticks;
35
36/* This prototype is added here to Avoid warnings */
37void Clock_isr(void *arg);
38
39static void generic_or1k_clock_at_tick(void)
40{
41  uint32_t TTMR;
42
43 /* For TTMR register,
44  * The least significant 28 bits are the number of clock cycles
45  * before generating a tick timer interrupt. While the most
46  * significant 4 bits are used for mode configuration, tick timer
47  * interrupt enable and pending interrupts status.
48  */
49  TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
50           (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK)
51         ) & ~(CPU_OR1K_SPR_TTMR_IP);
52
53  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
54  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
55
56  cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT;
57}
58
59static void generic_or1k_clock_handler_install(proc_ptr new_isr)
60{
61  rtems_status_code sc = RTEMS_SUCCESSFUL;
62  _CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER,
63                          new_isr,
64                          NULL);
65
66  if (sc != RTEMS_SUCCESSFUL) {
67    rtems_fatal_error_occurred(0xdeadbeef);
68  }
69}
70
71static uint32_t or1ksim_get_timecount(struct timecounter *tc)
72{
73  uint32_t ticks_since_last_timer_interrupt;
74
75  ticks_since_last_timer_interrupt = _OR1K_mfspr(CPU_OR1K_SPR_TTCR);
76
77  return cpu_counter_ticks + ticks_since_last_timer_interrupt;
78}
79
80CPU_Counter_ticks _CPU_Counter_read(void)
81{
82  return or1ksim_get_timecount(NULL);
83}
84
85static void generic_or1k_clock_initialize(void)
86{
87  uint64_t frequency = (1000000000 / OR1K_CLOCK_CYCLE_TIME_NANOSECONDS);
88  uint32_t TTMR;
89
90 /* For TTMR register,
91  * The least significant 28 bits are the number of clock cycles
92  * before generating a tick timer interrupt. While the most
93  * significant 4 bits are used for mode configuration, tick timer
94  * interrupt enable and pending interrupts status.
95  */
96
97  /* FIXME: Long interval should pass since initializing the tick timer
98   * registers fires exceptions dispite interrupts has not been enabled yet.
99   */
100  TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
101           (0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK)
102         ) & ~(CPU_OR1K_SPR_TTMR_IP);
103
104  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
105  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
106
107  /* Initialize timecounter */
108  or1ksim_tc.tc_get_timecount = or1ksim_get_timecount;
109  or1ksim_tc.tc_counter_mask = 0xffffffff;
110  or1ksim_tc.tc_frequency = frequency;
111  or1ksim_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
112  rtems_timecounter_install(&or1ksim_tc);
113}
114
115static void generic_or1k_clock_cleanup(void)
116{
117 uint32_t sr;
118
119  sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
120
121  /* Disable tick timer exceptions */
122  _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)
123  & ~CPU_OR1K_SPR_SR_TEE);
124
125  /* Invalidate tick timer config registers */
126  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
127  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, 0);
128}
129
130CPU_Counter_ticks _CPU_Counter_difference(
131  CPU_Counter_ticks second,
132  CPU_Counter_ticks first
133)
134{
135  return second - first;
136}
137
138#define Clock_driver_support_at_tick() generic_or1k_clock_at_tick()
139
140#define Clock_driver_support_initialize_hardware() generic_or1k_clock_initialize()
141
142#define Clock_driver_support_install_isr(isr) \
143  generic_or1k_clock_handler_install(isr)
144
145#define Clock_driver_support_shutdown_hardware() generic_or1k_clock_cleanup()
146
147#include "../../../shared/clockdrv_shell.h"
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