1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_clock |
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5 | * |
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6 | * @brief or1k clock support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * generic_or1k Clock driver |
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11 | * |
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12 | * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com> |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE |
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17 | */ |
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18 | |
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19 | #include <rtems.h> |
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20 | #include <bsp.h> |
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21 | #include <bsp/irq.h> |
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22 | #include <bsp/generic_or1k.h> |
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23 | #include <rtems/score/cpu.h> |
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24 | #include <rtems/score/or1k-utility.h> |
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25 | #include <rtems/timecounter.h> |
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26 | |
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27 | /* The number of clock cycles before generating a tick timer interrupt. */ |
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28 | #define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 0x09ED9 |
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29 | #define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS 10 |
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30 | |
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31 | static struct timecounter or1ksim_tc; |
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32 | |
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33 | /* CPU counter */ |
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34 | static CPU_Counter_ticks cpu_counter_ticks; |
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35 | |
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36 | /* This prototype is added here to Avoid warnings */ |
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37 | void Clock_isr(void *arg); |
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38 | |
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39 | static void generic_or1k_clock_at_tick(void) |
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40 | { |
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41 | uint32_t TTMR; |
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42 | |
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43 | /* For TTMR register, |
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44 | * The least significant 28 bits are the number of clock cycles |
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45 | * before generating a tick timer interrupt. While the most |
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46 | * significant 4 bits are used for mode configuration, tick timer |
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47 | * interrupt enable and pending interrupts status. |
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48 | */ |
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49 | TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE | |
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50 | (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK) |
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51 | ) & ~(CPU_OR1K_SPR_TTMR_IP); |
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52 | |
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53 | _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR); |
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54 | _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); |
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55 | |
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56 | cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; |
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57 | } |
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58 | |
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59 | static void generic_or1k_clock_handler_install(proc_ptr new_isr) |
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60 | { |
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61 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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62 | _CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER, |
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63 | new_isr, |
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64 | NULL); |
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65 | |
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66 | if (sc != RTEMS_SUCCESSFUL) { |
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67 | rtems_fatal_error_occurred(0xdeadbeef); |
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68 | } |
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69 | } |
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70 | |
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71 | static uint32_t or1ksim_get_timecount(struct timecounter *tc) |
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72 | { |
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73 | uint32_t ticks_since_last_timer_interrupt; |
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74 | |
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75 | ticks_since_last_timer_interrupt = _OR1K_mfspr(CPU_OR1K_SPR_TTCR); |
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76 | |
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77 | return cpu_counter_ticks + ticks_since_last_timer_interrupt; |
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78 | } |
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79 | |
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80 | CPU_Counter_ticks _CPU_Counter_read(void) |
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81 | { |
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82 | return or1ksim_get_timecount(NULL); |
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83 | } |
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84 | |
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85 | static void generic_or1k_clock_initialize(void) |
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86 | { |
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87 | uint64_t frequency = (1000000000 / OR1K_CLOCK_CYCLE_TIME_NANOSECONDS); |
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88 | uint32_t TTMR; |
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89 | |
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90 | /* For TTMR register, |
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91 | * The least significant 28 bits are the number of clock cycles |
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92 | * before generating a tick timer interrupt. While the most |
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93 | * significant 4 bits are used for mode configuration, tick timer |
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94 | * interrupt enable and pending interrupts status. |
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95 | */ |
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96 | |
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97 | /* FIXME: Long interval should pass since initializing the tick timer |
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98 | * registers fires exceptions dispite interrupts has not been enabled yet. |
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99 | */ |
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100 | TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE | |
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101 | (0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK) |
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102 | ) & ~(CPU_OR1K_SPR_TTMR_IP); |
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103 | |
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104 | _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR); |
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105 | _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); |
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106 | |
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107 | /* Initialize timecounter */ |
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108 | or1ksim_tc.tc_get_timecount = or1ksim_get_timecount; |
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109 | or1ksim_tc.tc_counter_mask = 0xffffffff; |
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110 | or1ksim_tc.tc_frequency = frequency; |
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111 | or1ksim_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
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112 | rtems_timecounter_install(&or1ksim_tc); |
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113 | } |
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114 | |
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115 | static void generic_or1k_clock_cleanup(void) |
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116 | { |
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117 | uint32_t sr; |
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118 | |
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119 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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120 | |
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121 | /* Disable tick timer exceptions */ |
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122 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE) |
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123 | & ~CPU_OR1K_SPR_SR_TEE); |
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124 | |
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125 | /* Invalidate tick timer config registers */ |
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126 | _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); |
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127 | _OR1K_mtspr(CPU_OR1K_SPR_TTMR, 0); |
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128 | } |
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129 | |
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130 | CPU_Counter_ticks _CPU_Counter_difference( |
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131 | CPU_Counter_ticks second, |
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132 | CPU_Counter_ticks first |
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133 | ) |
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134 | { |
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135 | return second - first; |
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136 | } |
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137 | |
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138 | #define Clock_driver_support_at_tick() generic_or1k_clock_at_tick() |
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139 | |
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140 | #define Clock_driver_support_initialize_hardware() generic_or1k_clock_initialize() |
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141 | |
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142 | #define Clock_driver_support_install_isr(isr) \ |
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143 | generic_or1k_clock_handler_install(isr) |
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144 | |
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145 | #define Clock_driver_support_shutdown_hardware() generic_or1k_clock_cleanup() |
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146 | |
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147 | #include "../../../shared/clockdrv_shell.h" |
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