source: rtems/c/src/lib/libbsp/or1k/generic_or1k/clock/clockdrv.c @ 75acd9e

4.11
Last change on this file since 75acd9e was 75acd9e, checked in by Alexander Krutwig <alexander.krutwig@…>, on Apr 1, 2015 at 1:33:25 PM

bsps: Convert clock drivers to use a timecounter

Update #2271.

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup bsp_clock
5 *
6 * @brief or1k clock support.
7 */
8
9/*
10 * generic_or1k Clock driver
11 *
12 * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
13 *
14 * The license and distribution terms for this file may be
15 * found in the file LICENSE in this distribution or at
16 * http://www.rtems.org/license/LICENSE
17 */
18
19#include <rtems.h>
20#include <bsp.h>
21#include <bsp/irq.h>
22#include <bsp/generic_or1k.h>
23#include <rtems/score/cpu.h>
24#include <rtems/score/or1k-utility.h>
25#include <rtems/timecounter.h>
26
27/* The number of clock cycles before generating a tick timer interrupt. */
28#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT     0x09ED9
29#define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS     10
30
31static struct timecounter or1ksim_tc;
32
33/* CPU counter */
34static CPU_Counter_ticks cpu_counter_ticks;
35
36/* This prototype is added here to Avoid warnings */
37void Clock_isr(void *arg);
38
39static void generic_or1k_clock_at_tick(void)
40{
41  uint32_t TTMR;
42
43 /* For TTMR register,
44  * The least significant 28 bits are the number of clock cycles
45  * before generating a tick timer interrupt. While the most
46  * significant 4 bits are used for mode configuration, tick timer
47  * interrupt enable and pending interrupts status.
48  */
49  TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
50           (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK)
51         ) & ~(CPU_OR1K_SPR_TTMR_IP);
52
53  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
54  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
55
56  cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT;
57}
58
59static void generic_or1k_clock_handler_install(
60  proc_ptr new_isr,
61   proc_ptr old_isr
62)
63{
64  rtems_status_code sc = RTEMS_SUCCESSFUL;
65  old_isr = NULL;
66  _CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER,
67                          new_isr,
68                          old_isr);
69
70  if (sc != RTEMS_SUCCESSFUL) {
71    rtems_fatal_error_occurred(0xdeadbeef);
72  }
73}
74
75static uint32_t or1ksim_get_timecount(struct timecounter *tc)
76{
77  uint32_t ticks_since_last_timer_interrupt;
78
79  ticks_since_last_timer_interrupt = _OR1K_mfspr(CPU_OR1K_SPR_TTCR);
80
81  return cpu_counter_ticks + ticks_since_last_timer_interrupt;
82}
83
84CPU_Counter_ticks _CPU_Counter_read(void)
85{
86  return or1ksim_get_timecount(NULL);
87}
88
89static void generic_or1k_clock_initialize(void)
90{
91  uint64_t frequency = (1000000000 / OR1K_CLOCK_CYCLE_TIME_NANOSECONDS);
92  uint32_t TTMR;
93
94 /* For TTMR register,
95  * The least significant 28 bits are the number of clock cycles
96  * before generating a tick timer interrupt. While the most
97  * significant 4 bits are used for mode configuration, tick timer
98  * interrupt enable and pending interrupts status.
99  */
100
101  /* FIXME: Long interval should pass since initializing the tick timer
102   * registers fires exceptions dispite interrupts has not been enabled yet.
103   */
104  TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
105           (0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK)
106         ) & ~(CPU_OR1K_SPR_TTMR_IP);
107
108  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
109  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
110
111  /* Initialize timecounter */
112  or1ksim_tc.tc_get_timecount = or1ksim_get_timecount;
113  or1ksim_tc.tc_counter_mask = 0xffffffff;
114  or1ksim_tc.tc_frequency = frequency;
115  or1ksim_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
116  rtems_timecounter_install(&or1ksim_tc);
117}
118
119static void generic_or1k_clock_cleanup(void)
120{
121 uint32_t sr;
122
123  sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
124
125  /* Disable tick timer exceptions */
126  _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)
127  & ~CPU_OR1K_SPR_SR_TEE);
128
129  /* Invalidate tick timer config registers */
130  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
131  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, 0);
132}
133
134CPU_Counter_ticks _CPU_Counter_difference(
135  CPU_Counter_ticks second,
136  CPU_Counter_ticks first
137)
138{
139  return second - first;
140}
141
142#define Clock_driver_support_at_tick() generic_or1k_clock_at_tick()
143
144#define Clock_driver_support_initialize_hardware() generic_or1k_clock_initialize()
145
146#define Clock_driver_support_install_isr(isr, old_isr) \
147  do {                                                 \
148    old_isr = NULL;                                    \
149    generic_or1k_clock_handler_install(isr, old_isr);       \
150  } while (0)
151
152#define Clock_driver_support_shutdown_hardware() generic_or1k_clock_cleanup()
153
154#include "../../../shared/clockdrv_shell.h"
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