[fd57015] | 1 | /** |
---|
| 2 | * @file |
---|
| 3 | * |
---|
| 4 | * @ingroup bsp_clock |
---|
| 5 | * |
---|
[3d597c0] | 6 | * @brief or1k clock support. |
---|
[fd57015] | 7 | */ |
---|
| 8 | |
---|
| 9 | /* |
---|
[3d597c0] | 10 | * generic_or1k Clock driver |
---|
[fd57015] | 11 | * |
---|
[3d597c0] | 12 | * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com> |
---|
[fd57015] | 13 | * |
---|
| 14 | * The license and distribution terms for this file may be |
---|
| 15 | * found in the file LICENSE in this distribution or at |
---|
| 16 | * http://www.rtems.org/license/LICENSE |
---|
| 17 | */ |
---|
| 18 | |
---|
| 19 | #include <rtems.h> |
---|
| 20 | #include <bsp.h> |
---|
| 21 | #include <bsp/irq.h> |
---|
[3d597c0] | 22 | #include <bsp/generic_or1k.h> |
---|
[fd57015] | 23 | #include <rtems/score/cpu.h> |
---|
| 24 | #include <rtems/score/or1k-utility.h> |
---|
[75acd9e] | 25 | #include <rtems/timecounter.h> |
---|
[fd57015] | 26 | |
---|
| 27 | /* The number of clock cycles before generating a tick timer interrupt. */ |
---|
[5f56d267] | 28 | #define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 0x09ED9 |
---|
[3d597c0] | 29 | #define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS 10 |
---|
[fd57015] | 30 | |
---|
[75acd9e] | 31 | static struct timecounter or1ksim_tc; |
---|
| 32 | |
---|
[d2c76160] | 33 | /* CPU counter */ |
---|
| 34 | static CPU_Counter_ticks cpu_counter_ticks; |
---|
| 35 | |
---|
[fd57015] | 36 | /* This prototype is added here to Avoid warnings */ |
---|
| 37 | void Clock_isr(void *arg); |
---|
| 38 | |
---|
[3d597c0] | 39 | static void generic_or1k_clock_at_tick(void) |
---|
[fd57015] | 40 | { |
---|
| 41 | uint32_t TTMR; |
---|
| 42 | |
---|
| 43 | /* For TTMR register, |
---|
| 44 | * The least significant 28 bits are the number of clock cycles |
---|
| 45 | * before generating a tick timer interrupt. While the most |
---|
| 46 | * significant 4 bits are used for mode configuration, tick timer |
---|
| 47 | * interrupt enable and pending interrupts status. |
---|
| 48 | */ |
---|
| 49 | TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE | |
---|
| 50 | (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK) |
---|
| 51 | ) & ~(CPU_OR1K_SPR_TTMR_IP); |
---|
| 52 | |
---|
| 53 | _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR); |
---|
| 54 | _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); |
---|
[d2c76160] | 55 | |
---|
| 56 | cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; |
---|
[fd57015] | 57 | } |
---|
| 58 | |
---|
[3d597c0] | 59 | static void generic_or1k_clock_handler_install( |
---|
| 60 | proc_ptr new_isr, |
---|
| 61 | proc_ptr old_isr |
---|
| 62 | ) |
---|
[fd57015] | 63 | { |
---|
| 64 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
---|
| 65 | old_isr = NULL; |
---|
| 66 | _CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER, |
---|
| 67 | new_isr, |
---|
| 68 | old_isr); |
---|
| 69 | |
---|
| 70 | if (sc != RTEMS_SUCCESSFUL) { |
---|
| 71 | rtems_fatal_error_occurred(0xdeadbeef); |
---|
| 72 | } |
---|
| 73 | } |
---|
| 74 | |
---|
[75acd9e] | 75 | static uint32_t or1ksim_get_timecount(struct timecounter *tc) |
---|
| 76 | { |
---|
| 77 | uint32_t ticks_since_last_timer_interrupt; |
---|
| 78 | |
---|
| 79 | ticks_since_last_timer_interrupt = _OR1K_mfspr(CPU_OR1K_SPR_TTCR); |
---|
| 80 | |
---|
| 81 | return cpu_counter_ticks + ticks_since_last_timer_interrupt; |
---|
| 82 | } |
---|
| 83 | |
---|
| 84 | CPU_Counter_ticks _CPU_Counter_read(void) |
---|
| 85 | { |
---|
| 86 | return or1ksim_get_timecount(NULL); |
---|
| 87 | } |
---|
| 88 | |
---|
[3d597c0] | 89 | static void generic_or1k_clock_initialize(void) |
---|
[fd57015] | 90 | { |
---|
[75acd9e] | 91 | uint64_t frequency = (1000000000 / OR1K_CLOCK_CYCLE_TIME_NANOSECONDS); |
---|
[5f56d267] | 92 | uint32_t TTMR; |
---|
[fd57015] | 93 | |
---|
[5f56d267] | 94 | /* For TTMR register, |
---|
| 95 | * The least significant 28 bits are the number of clock cycles |
---|
| 96 | * before generating a tick timer interrupt. While the most |
---|
| 97 | * significant 4 bits are used for mode configuration, tick timer |
---|
| 98 | * interrupt enable and pending interrupts status. |
---|
| 99 | */ |
---|
[fd57015] | 100 | |
---|
[5f56d267] | 101 | /* FIXME: Long interval should pass since initializing the tick timer |
---|
| 102 | * registers fires exceptions dispite interrupts has not been enabled yet. |
---|
| 103 | */ |
---|
| 104 | TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE | |
---|
| 105 | (0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK) |
---|
| 106 | ) & ~(CPU_OR1K_SPR_TTMR_IP); |
---|
| 107 | |
---|
| 108 | _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR); |
---|
| 109 | _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); |
---|
[d2c76160] | 110 | |
---|
[75acd9e] | 111 | /* Initialize timecounter */ |
---|
| 112 | or1ksim_tc.tc_get_timecount = or1ksim_get_timecount; |
---|
| 113 | or1ksim_tc.tc_counter_mask = 0xffffffff; |
---|
| 114 | or1ksim_tc.tc_frequency = frequency; |
---|
| 115 | or1ksim_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
---|
| 116 | rtems_timecounter_install(&or1ksim_tc); |
---|
[fd57015] | 117 | } |
---|
| 118 | |
---|
[75acd9e] | 119 | static void generic_or1k_clock_cleanup(void) |
---|
[fd57015] | 120 | { |
---|
[5f56d267] | 121 | uint32_t sr; |
---|
| 122 | |
---|
| 123 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
---|
| 124 | |
---|
| 125 | /* Disable tick timer exceptions */ |
---|
| 126 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE) |
---|
| 127 | & ~CPU_OR1K_SPR_SR_TEE); |
---|
| 128 | |
---|
| 129 | /* Invalidate tick timer config registers */ |
---|
| 130 | _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); |
---|
| 131 | _OR1K_mtspr(CPU_OR1K_SPR_TTMR, 0); |
---|
[fd57015] | 132 | } |
---|
| 133 | |
---|
[d2c76160] | 134 | CPU_Counter_ticks _CPU_Counter_difference( |
---|
| 135 | CPU_Counter_ticks second, |
---|
| 136 | CPU_Counter_ticks first |
---|
| 137 | ) |
---|
| 138 | { |
---|
| 139 | return second - first; |
---|
| 140 | } |
---|
[75acd9e] | 141 | |
---|
[3d597c0] | 142 | #define Clock_driver_support_at_tick() generic_or1k_clock_at_tick() |
---|
[fd57015] | 143 | |
---|
[3d597c0] | 144 | #define Clock_driver_support_initialize_hardware() generic_or1k_clock_initialize() |
---|
[fd57015] | 145 | |
---|
| 146 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
---|
| 147 | do { \ |
---|
| 148 | old_isr = NULL; \ |
---|
[3d597c0] | 149 | generic_or1k_clock_handler_install(isr, old_isr); \ |
---|
[fd57015] | 150 | } while (0) |
---|
| 151 | |
---|
[3d597c0] | 152 | #define Clock_driver_support_shutdown_hardware() generic_or1k_clock_cleanup() |
---|
[fd57015] | 153 | |
---|
| 154 | #include "../../../shared/clockdrv_shell.h" |
---|