1 | /* |
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2 | |
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3 | Based upon IDT provided code with the following release: |
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4 | |
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5 | This source code has been made available to you by IDT on an AS-IS |
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6 | basis. Anyone receiving this source is licensed under IDT copyrights |
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7 | to use it in any way he or she deems fit, including copying it, |
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8 | modifying it, compiling it, and redistributing it either with or |
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9 | without modifications. No license under IDT patents or patent |
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10 | applications is to be implied by the copyright license. |
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11 | |
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12 | Any user of this software should understand that IDT cannot provide |
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13 | technical support for this software and will not be responsible for |
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14 | any consequences resulting from the use of this software. |
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15 | |
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16 | Any person who transfers this source code or any derivative work must |
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17 | include the IDT copyright notice, this paragraph, and the preceeding |
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18 | two paragraphs in the transferred software. |
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19 | |
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20 | COPYRIGHT IDT CORPORATION 1996 |
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21 | LICENSED MATERIAL - PROGRAM PROPERTY OF IDT |
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22 | |
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23 | $Id$ |
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24 | */ |
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25 | |
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26 | |
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27 | /* |
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28 | ** idttlb.s - fetch the registers associated with and the contents |
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29 | ** of the tlb. |
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30 | ** |
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31 | */ |
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32 | /* 950308: Ketan patched a few tlb functions that would not have worked.*/ |
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33 | #include <iregdef.h> |
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34 | #include <idtcpu.h> |
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35 | #include <idtmon.h> |
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36 | |
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37 | |
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38 | .text |
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39 | |
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40 | #if defined(CPU_R3000) |
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41 | /* |
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42 | ** ret_tlblo -- returns the 'entrylo' contents for the TLB |
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43 | ** 'c' callable - as ret_tlblo(index) - where index is the |
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44 | ** tlb entry to return the lo value for - if called from assembly |
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45 | ** language then index should be in register a0. |
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46 | */ |
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47 | FRAME(ret_tlblo,sp,0,ra) |
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48 | .set noreorder |
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49 | mfc0 t0,C0_SR # save sr |
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50 | nop |
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51 | and t0,~SR_PE # dont inadvertantly clear PE |
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52 | mtc0 zero,C0_SR # clear interrupts |
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53 | mfc0 t1,C0_TLBHI # save pid |
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54 | sll a0,TLBINX_INXSHIFT # position index |
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55 | mtc0 a0,C0_INX # write to index register |
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56 | nop |
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57 | tlbr # put tlb entry in entrylo and hi |
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58 | nop |
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59 | mfc0 v0,C0_TLBLO # get the requested entry lo |
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60 | mtc0 t1,C0_TLBHI # restore pid |
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61 | mtc0 t0,C0_SR # restore status register |
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62 | j ra |
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63 | nop |
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64 | .set reorder |
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65 | ENDFRAME(ret_tlblo) |
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66 | #endif |
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67 | #if defined(CPU_R4000) |
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68 | /* |
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69 | ** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB |
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70 | ** 'c' callable - as ret_tlblo(index) - where index is the |
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71 | ** tlb entry to return the lo value for - if called from assembly |
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72 | ** language then index should be in register a0. |
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73 | */ |
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74 | FRAME(ret_tlblo0,sp,0,ra) |
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75 | mfc0 t0,C0_SR # save sr |
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76 | mtc0 zero,C0_SR # clear interrupts |
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77 | mfc0 t1,C0_TLBHI # save pid |
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78 | mtc0 a0,C0_INX # write to index register |
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79 | .set noreorder |
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80 | nop; nop; nop; nop; nop; nop; nop; nop |
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81 | .set reorder |
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82 | tlbr # put tlb entry in entrylo and hi |
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83 | .set noreorder |
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84 | nop; nop; nop; nop; nop; nop; nop; nop |
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85 | .set reorder |
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86 | mfc0 v0,C0_TLBLO0 # get the requested entry lo |
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87 | mtc0 t1,C0_TLBHI # restore pid |
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88 | mtc0 t0,C0_SR # restore status register |
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89 | j ra |
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90 | ENDFRAME(ret_tlblo0) |
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91 | |
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92 | FRAME(ret_tlblo1,sp,0,ra) |
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93 | mfc0 t0,C0_SR # save sr |
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94 | mtc0 zero,C0_SR # clear interrupts |
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95 | mfc0 t1,C0_TLBHI # save pid |
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96 | mtc0 a0,C0_INX # write to index register |
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97 | .set noreorder |
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98 | nop; nop; nop; nop; nop; nop; nop; nop |
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99 | .set reorder |
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100 | tlbr # put tlb entry in entrylo and hi |
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101 | .set noreorder |
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102 | nop; nop; nop; nop; nop; nop; nop; nop |
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103 | .set reorder |
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104 | mfc0 v0,C0_TLBLO1 # get the requested entry lo |
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105 | mtc0 t1,C0_TLBHI # restore pid |
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106 | mtc0 t0,C0_SR # restore status register |
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107 | j ra |
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108 | ENDFRAME(ret_tlblo1) |
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109 | |
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110 | /* |
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111 | ** ret_pagemask(index) -- return pagemask contents of tlb entry "index" |
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112 | */ |
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113 | FRAME(ret_pagemask,sp,0,ra) |
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114 | mfc0 t0,C0_SR # save sr |
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115 | mtc0 zero,C0_SR # disable interrupts |
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116 | mfc0 t1,C0_TLBHI # save current pid |
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117 | mtc0 a0,C0_INX # drop it in C0 register |
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118 | .set noreorder |
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119 | nop; nop; nop; nop; nop; nop; nop; nop |
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120 | .set reorder |
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121 | tlbr # read entry to entry hi/lo |
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122 | .set noreorder |
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123 | nop; nop; nop; nop; nop; nop; nop; nop |
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124 | .set reorder |
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125 | mfc0 v0,C0_PAGEMASK # to return value |
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126 | mtc0 t1,C0_TLBHI # restore current pid |
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127 | mtc0 t0,C0_SR # restore sr |
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128 | j ra |
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129 | ENDFRAME(ret_pagemask) |
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130 | |
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131 | /* |
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132 | ** ret_tlbwired(void) -- return wired register |
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133 | */ |
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134 | FRAME(ret_tlbwired,sp,0,ra) |
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135 | mfc0 v0,C0_WIRED |
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136 | j ra |
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137 | ENDFRAME(ret_tlbwired) |
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138 | #endif |
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139 | |
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140 | /* |
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141 | ** ret_tlbhi -- return the tlb entry high content for tlb entry |
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142 | ** index |
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143 | */ |
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144 | FRAME(ret_tlbhi,sp,0,ra) |
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145 | #if defined(CPU_R3000) |
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146 | .set noreorder |
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147 | mfc0 t0,C0_SR # save sr |
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148 | nop |
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149 | and t0,~SR_PE |
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150 | mtc0 zero,C0_SR # disable interrupts |
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151 | mfc0 t1,C0_TLBHI # save current pid |
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152 | sll a0,TLBINX_INXSHIFT # position index |
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153 | mtc0 a0,C0_INX # drop it in C0 register |
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154 | nop |
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155 | tlbr # read entry to entry hi/lo |
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156 | nop |
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157 | mfc0 v0,C0_TLBHI # to return value |
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158 | mtc0 t1,C0_TLBHI # restore current pid |
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159 | mtc0 t0,C0_SR # restore sr |
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160 | j ra |
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161 | nop |
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162 | .set reorder |
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163 | #endif |
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164 | #if defined(CPU_R4000) |
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165 | mfc0 t0,C0_SR # save sr |
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166 | mtc0 zero,C0_SR # disable interrupts |
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167 | mfc0 t1,C0_TLBHI # save current pid |
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168 | mtc0 a0,C0_INX # drop it in C0 register |
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169 | .set noreorder |
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170 | nop; nop; nop; nop; nop; nop; nop; nop |
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171 | .set reorder |
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172 | tlbr # read entry to entry hi/lo0/lo1/mask |
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173 | .set noreorder |
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174 | nop; nop; nop; nop; nop; nop; nop; nop |
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175 | .set reorder |
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176 | mfc0 v0,C0_TLBHI # to return value |
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177 | mtc0 t1,C0_TLBHI # restore current pid |
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178 | mtc0 t0,C0_SR # restore sr |
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179 | j ra |
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180 | #endif |
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181 | ENDFRAME(ret_tlbhi) |
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182 | |
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183 | /* |
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184 | ** ret_tlbpid() -- return tlb pid contained in the current entry hi |
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185 | */ |
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186 | FRAME(ret_tlbpid,sp,0,ra) |
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187 | #if defined(CPU_R3000) |
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188 | .set noreorder |
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189 | mfc0 v0,C0_TLBHI # fetch tlb high |
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190 | nop |
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191 | and v0,TLBHI_PIDMASK # isolate and position |
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192 | srl v0,TLBHI_PIDSHIFT |
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193 | j ra |
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194 | nop |
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195 | .set reorder |
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196 | #endif |
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197 | #if defined(CPU_R4000) |
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198 | mfc0 v0,C0_TLBHI # to return value |
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199 | nop |
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200 | and v0,TLBHI_PIDMASK |
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201 | j ra |
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202 | #endif |
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203 | ENDFRAME(ret_tlbpid) |
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204 | |
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205 | /* |
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206 | ** tlbprobe(address, pid) -- probe the tlb to see if address is currently |
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207 | ** mapped |
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208 | ** a0 = vpn - virtual page numbers are 0=0 1=0x1000, 2=0x2000... |
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209 | ** virtual page numbers for the r3000 are in |
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210 | ** entry hi bits 31-12 |
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211 | ** a1 = pid - this is a process id ranging from 0 to 63 |
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212 | ** this process id is shifted left 6 bits and or'ed into |
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213 | ** the entry hi register |
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214 | ** returns an index value (0-63) if successful -1 -f not |
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215 | */ |
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216 | FRAME(tlbprobe,sp,0,ra) |
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217 | #if defined(CPU_R3000) |
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218 | .set noreorder |
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219 | mfc0 t0,C0_SR /* fetch status reg */ |
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220 | and a0,TLBHI_VPNMASK /* isolate just the vpn */ |
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221 | and t0,~SR_PE /* don't inadvertantly clear pe */ |
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222 | mtc0 zero,C0_SR |
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223 | mfc0 t1,C0_TLBHI |
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224 | sll a1,TLBHI_PIDSHIFT /* possition the pid */ |
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225 | and a1,TLBHI_PIDMASK |
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226 | or a0,a1 /* build entry hi value */ |
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227 | mtc0 a0,C0_TLBHI |
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228 | nop |
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229 | tlbp /* do the probe */ |
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230 | nop |
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231 | mfc0 v1,C0_INX |
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232 | li v0,-1 |
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233 | bltz v1,1f |
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234 | nop |
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235 | sra v0,v1,TLBINX_INXSHIFT /* get index positioned for return */ |
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236 | 1: |
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237 | mtc0 t1,C0_TLBHI /* restore tlb hi */ |
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238 | mtc0 t0,C0_SR /* restore the status reg */ |
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239 | j ra |
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240 | nop |
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241 | .set reorder |
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242 | #endif |
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243 | #if defined(CPU_R4000) |
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244 | mfc0 t0,C0_SR # save sr |
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245 | mtc0 zero,C0_SR # disable interrupts |
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246 | mfc0 t1,C0_TLBHI # save current pid |
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247 | and a0,TLBHI_VPN2MASK # construct tlbhi for probe |
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248 | and a1,TLBHI_PIDMASK |
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249 | or a0,a1 |
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250 | mtc0 a0,C0_TLBHI |
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251 | .set noreorder |
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252 | nop; nop; nop; nop; nop; nop; nop; nop |
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253 | .set reorder |
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254 | tlbp # probe entry to entry hi/lo0/lo1/mask |
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255 | .set noreorder |
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256 | nop; nop; nop; nop; nop; nop; nop; nop |
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257 | .set reorder |
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258 | mfc0 v1,C0_INX |
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259 | li v0,-1 |
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260 | bltz v1,1f |
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261 | move v0,v1 |
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262 | 1: mtc0 t1,C0_TLBHI # restore current pid |
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263 | mtc0 t0,C0_SR # restore sr |
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264 | j ra |
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265 | #endif |
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266 | ENDFRAME(tlbprobe) |
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267 | |
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268 | /* |
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269 | ** resettlb(index) Invalidate the TLB entry specified by index |
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270 | */ |
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271 | FRAME(resettlb,sp,0,ra) |
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272 | #if defined(CPU_R3000) |
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273 | .set noreorder |
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274 | mfc0 t0,C0_TLBHI # fetch the current hi |
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275 | mfc0 v0,C0_SR # fetch the status reg. |
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276 | li t2,K0BASE&TLBHI_VPNMASK |
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277 | and v0,~SR_PE # dont inadvertantly clear PE |
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278 | mtc0 zero,C0_SR |
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279 | mtc0 t2,C0_TLBHI # set up tlbhi |
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280 | mtc0 zero,C0_TLBLO |
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281 | sll a0,TLBINX_INXSHIFT |
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282 | mtc0 a0,C0_INX |
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283 | nop |
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284 | tlbwi # do actual invalidate |
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285 | nop |
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286 | mtc0 t0,C0_TLBHI |
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287 | mtc0 v0,C0_SR |
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288 | j ra |
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289 | nop |
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290 | .set reorder |
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291 | #endif |
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292 | #if defined(CPU_R4000) |
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293 | li t2,K0BASE&TLBHI_VPN2MASK |
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294 | mfc0 t0,C0_TLBHI # save current TLBHI |
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295 | mfc0 v0,C0_SR # save SR and disable interrupts |
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296 | mtc0 zero,C0_SR |
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297 | mtc0 t2,C0_TLBHI # invalidate entry |
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298 | mtc0 zero,C0_TLBLO0 |
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299 | mtc0 zero,C0_TLBLO1 |
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300 | mtc0 a0,C0_INX |
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301 | .set noreorder |
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302 | nop; nop; nop; nop; nop; nop; nop; nop |
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303 | .set reorder |
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304 | tlbwi |
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305 | .set noreorder |
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306 | nop; nop; nop; nop; nop; nop; nop; nop |
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307 | .set reorder |
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308 | mtc0 t0,C0_TLBHI |
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309 | mtc0 v0,C0_SR |
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310 | j ra |
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311 | #endif |
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312 | ENDFRAME(resettlb) |
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313 | |
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314 | #if defined(CPU_R3000) |
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315 | /* |
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316 | ** Setup TLB entry |
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317 | ** |
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318 | ** map_tlb(index, tlbhi, phypage) |
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319 | ** a0 = TLB entry index |
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320 | ** a1 = virtual page number and PID |
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321 | ** a2 = physical page |
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322 | */ |
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323 | FRAME(map_tlb,sp,0,ra) |
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324 | .set noreorder |
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325 | sll a0,TLBINX_INXSHIFT |
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326 | mfc0 v0,C0_SR # fetch the current status |
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327 | mfc0 a3,C0_TLBHI # save the current hi |
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328 | and v0,~SR_PE # dont inadvertantly clear parity |
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329 | |
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330 | mtc0 zero,C0_SR |
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331 | mtc0 a1,C0_TLBHI # set the hi entry |
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332 | mtc0 a2,C0_TLBLO # set the lo entry |
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333 | mtc0 a0,C0_INX # load the index |
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334 | nop |
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335 | tlbwi # put the hi/lo in tlb entry indexed |
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336 | nop |
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337 | mtc0 a3,C0_TLBHI # put back the tlb hi reg |
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338 | mtc0 v0,C0_SR # restore the status register |
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339 | j ra |
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340 | nop |
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341 | .set reorder |
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342 | ENDFRAME(map_tlb) |
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343 | #endif |
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344 | #if defined(CPU_R4000) |
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345 | /* |
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346 | ** Setup R4000 TLB entry |
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347 | ** |
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348 | ** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd) |
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349 | ** a0 = TLB entry index and page mask |
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350 | ** a1 = virtual page number and PID |
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351 | ** a2 = pte -- contents of even pte |
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352 | ** a3 = pte -- contents of odd pte |
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353 | */ |
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354 | FRAME(map_tlb4000,sp,0,ra) |
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355 | and t2,a0,TLBPGMASK_MASK |
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356 | and a0,TLBINX_INXMASK |
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357 | mfc0 t1,C0_TLBHI # save current TLBPID |
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358 | mfc0 v0,C0_SR # save SR and disable interrupts |
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359 | mtc0 zero,C0_SR |
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360 | mtc0 t2,C0_PAGEMASK # set |
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361 | mtc0 a1,C0_TLBHI # set VPN and TLBPID |
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362 | mtc0 a2,C0_TLBLO0 # set PPN and access bits |
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363 | mtc0 a3,C0_TLBLO1 # set PPN and access bits |
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364 | mtc0 a0,C0_INX # set INDEX to wired entry |
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365 | .set noreorder |
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366 | nop; nop; nop; nop; nop; nop; nop; nop |
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367 | .set reorder |
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368 | tlbwi # drop it in |
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369 | .set noreorder |
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370 | nop; nop; nop; nop; nop; nop; nop; nop |
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371 | .set reorder |
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372 | mtc0 t1,C0_TLBHI # restore TLBPID |
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373 | mtc0 v0,C0_SR # restore SR |
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374 | j ra |
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375 | ENDFRAME(map_tlb4000) |
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376 | #endif |
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377 | |
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378 | |
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379 | /* |
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380 | ** Set current TLBPID. This assumes PID is positioned correctly in reg. |
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381 | ** a0. |
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382 | */ |
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383 | FRAME(set_tlbpid,sp,0,ra) |
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384 | .set noreorder |
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385 | mtc0 a0,C0_TLBHI |
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386 | j ra |
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387 | nop |
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388 | .set reorder |
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389 | ENDFRAME(set_tlbpid) |
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390 | |
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