[f198c63] | 1 | /* |
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| 2 | |
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| 3 | Based upon IDT provided code with the following release: |
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| 4 | |
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| 5 | This source code has been made available to you by IDT on an AS-IS |
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| 6 | basis. Anyone receiving this source is licensed under IDT copyrights |
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| 7 | to use it in any way he or she deems fit, including copying it, |
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| 8 | modifying it, compiling it, and redistributing it either with or |
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| 9 | without modifications. No license under IDT patents or patent |
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| 10 | applications is to be implied by the copyright license. |
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| 11 | |
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| 12 | Any user of this software should understand that IDT cannot provide |
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| 13 | technical support for this software and will not be responsible for |
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| 14 | any consequences resulting from the use of this software. |
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| 15 | |
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| 16 | Any person who transfers this source code or any derivative work must |
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| 17 | include the IDT copyright notice, this paragraph, and the preceeding |
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| 18 | two paragraphs in the transferred software. |
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| 19 | |
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| 20 | COPYRIGHT IDT CORPORATION 1996 |
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| 21 | LICENSED MATERIAL - PROGRAM PROPERTY OF IDT |
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| 22 | |
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| 23 | */ |
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| 24 | |
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| 25 | /************************************************************************* |
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| 26 | ** |
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| 27 | ** Copyright 1991-95 Integrated Device Technology, Inc. |
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| 28 | ** All Rights Reserved |
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| 29 | ** |
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| 30 | ** idt_csu.S -- IDT stand alone startup code |
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| 31 | ** |
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| 32 | **************************************************************************/ |
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| 33 | #include <rtems/score/iregdef.h> |
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| 34 | #include <rtems/score/idtcpu.h> |
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| 35 | #include <rtems/score/idtmon.h> |
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| 36 | |
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| 37 | |
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| 38 | .extern _fbss,4 /* this is defined by the linker */ |
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| 39 | .extern end,4 /* this is defined by the linker */ |
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| 40 | |
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| 41 | .lcomm sim_mem_cfg_struct,12 |
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| 42 | |
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| 43 | .text |
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| 44 | |
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| 45 | |
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| 46 | #define TMP_STKSIZE 1024 |
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| 47 | |
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| 48 | /************************************************************************** |
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| 49 | ** |
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| 50 | ** start - Typicl standalone start up code required for R3000/R4000 |
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| 51 | ** |
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| 52 | ** |
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| 53 | ** 1) Initialize the STATUS Register |
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| 54 | ** a) Clear parity error bit |
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| 55 | ** b) Set co_processor 1 usable bit ON |
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| 56 | ** c) Clear all IntMask Enables |
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| 57 | ** d) Set kernel/disabled mode |
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| 58 | ** 2) Initialize Cause Register |
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| 59 | ** a) clear software interrupt bits |
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| 60 | ** 3) Determine FPU installed or not |
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| 61 | ** if not, clear CoProcessor 1 usable bit |
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| 62 | ** 4) Clear bss area |
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| 63 | ** 5) MUST allocate temporary stack until memory size determined |
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| 64 | ** It MUST be uncached to prevent overwriting when caches are cleared |
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| 65 | ** 6) Install exception handlers |
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| 66 | ** 7) Determine memory and cache sizes |
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| 67 | ** 8) Establish permanent stack (cached or uncached as defined by bss) |
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| 68 | ** 9) Flush Instruction and Data caches |
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| 69 | ** 10) If there is a Translation Lookaside Buffer, Clear the TLB |
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| 70 | ** 11) Execute initialization code if the IDT/c library is to be used |
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| 71 | ** |
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| 72 | ** 12) Jump to user's "main()" |
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| 73 | ** 13) Jump to promexit |
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| 74 | ** |
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| 75 | ** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. |
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| 76 | ** This is used to mark code specific to R3xxx or R4xxx processors. |
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| 77 | ** IDT/C 6.x defines __mips to be the ISA level for which we're |
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| 78 | ** generating code. This is used to make sure the stack etc. is |
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| 79 | ** double word aligned, when using -mips3 (default) or -mips2, |
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| 80 | ** when compiling with IDT/C6.x |
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| 81 | ** |
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| 82 | ***************************************************************************/ |
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| 83 | |
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| 84 | FRAME(start,sp,0,ra) |
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| 85 | |
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| 86 | .set noreorder |
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| 87 | #ifdef _R3000 |
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| 88 | li v0,SR_PE|SR_CU1 /* reset parity error and set */ |
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| 89 | /* cp1 usable */ |
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| 90 | #endif |
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| 91 | #ifdef _R4000 |
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| 92 | #if __mips==3 || defined(R4650) |
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| 93 | li v0,SR_CU1|SR_DE|SR_FR /* initally clear ERL, enable FPA 64bit regs*/ |
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| 94 | /* 4650: Need fr to be set anyway */ |
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| 95 | #else |
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| 96 | li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPA 32bit regs*/ |
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| 97 | #endif mips3 |
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| 98 | #endif |
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| 99 | |
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| 100 | mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ |
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| 101 | nop |
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| 102 | mtc0 zero,C0_CAUSE /* clear software interrupts */ |
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| 103 | nop |
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| 104 | |
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| 105 | #ifdef _R4000 |
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| 106 | li v0,CFG_C_NONCOHERENT # initialise default cache mode |
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| 107 | mtc0 v0,C0_CONFIG |
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| 108 | #endif |
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| 109 | |
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| 110 | /* |
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| 111 | ** check to see if an fpu is really plugged in |
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| 112 | */ |
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| 113 | li t3,0xaaaa5555 /* put a's and 5's in t3 */ |
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| 114 | mtc1 t3,fp0 /* try to write them into fp0 */ |
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| 115 | mtc1 zero,fp1 /* try to write zero in fp */ |
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| 116 | mfc1 t0,fp0 |
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| 117 | mfc1 t1,fp1 |
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| 118 | nop |
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| 119 | bne t0,t3,1f /* branch if no match */ |
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| 120 | nop |
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| 121 | bne t1,zero,1f /* double check for positive id */ |
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| 122 | nop |
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| 123 | /* We have a FPU. clear fcsr */ |
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| 124 | ctc1 zero, fcr31 |
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| 125 | j 2f /* status register already correct */ |
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| 126 | nop |
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| 127 | 1: |
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| 128 | #ifdef _R3000 |
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| 129 | li v0, SR_PE /* reset parity error/NO cp1 usable */ |
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| 130 | #endif |
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| 131 | |
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| 132 | #ifdef _R4000 |
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| 133 | li v0,SR_DE /* clear ERL and disable FPA */ |
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| 134 | #endif |
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| 135 | |
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| 136 | mtc0 v0, C0_SR /* reset status register */ |
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| 137 | 2: |
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| 138 | la gp, _gp |
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| 139 | |
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| 140 | la v0,_fbss /* clear bss before using it */ |
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| 141 | la v1,end /* end of bss */ |
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| 142 | 3: sw zero,0(v0) |
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| 143 | bltu v0,v1,3b |
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| 144 | add v0,4 |
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| 145 | |
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| 146 | |
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| 147 | /************************************************************************ |
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| 148 | ** |
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| 149 | ** Temporary Stack - needed to handle stack saves until |
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| 150 | ** memory size is determined and permanent stack set |
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| 151 | ** |
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| 152 | ** MUST be uncached to avoid confusion at cache |
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| 153 | ** switching during memory sizing |
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| 154 | ** |
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| 155 | *************************************************************************/ |
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| 156 | #if __mips==3 |
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| 157 | /* For MIPS 3, we need to be sure that the stack is aligned on a |
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| 158 | * double word boundary. |
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| 159 | */ |
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| 160 | andi t0, v0, 0x7 |
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| 161 | beqz t0, 11f /* Last three bits Zero, already aligned */ |
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| 162 | nop |
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| 163 | add v0, 4 |
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| 164 | 11: |
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| 165 | #endif |
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| 166 | |
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| 167 | or v0, K1BASE /* switch to uncached */ |
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| 168 | add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ |
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| 169 | sub v1, v1, (4*4) /* overhead */ |
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| 170 | move sp, v1 /* set sp to top of stack */ |
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| 171 | 4: sw zero, 0(v0) |
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| 172 | bltu v0, v1, 4b /* clear out temp stack */ |
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| 173 | add v0, 4 |
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| 174 | |
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| 175 | jal init_exc_vecs /* install exception handlers */ |
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| 176 | nop /* MUST do before memory probes */ |
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| 177 | |
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| 178 | la v0, 5f |
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| 179 | li v1, K1BASE /* force into uncached space */ |
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| 180 | or v0, v1 /* during memory/cache probes */ |
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| 181 | j v0 |
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| 182 | nop |
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| 183 | 5: |
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| 184 | la a0, sim_mem_cfg_struct |
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| 185 | jal sim_mem_cfg /* Make SIM call to get mem size */ |
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| 186 | nop |
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| 187 | la a0, sim_mem_cfg_struct |
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| 188 | lw a0, 0(a0) /* Get memory size from struct */ |
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| 189 | #ifdef _R3000 |
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| 190 | jal config_Icache |
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| 191 | nop |
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| 192 | jal config_Dcache /* determine size of D & I caches */ |
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| 193 | nop |
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| 194 | #endif |
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| 195 | #ifdef _R4000 |
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| 196 | jal config_cache /* determine size of D & I caches */ |
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| 197 | nop |
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| 198 | #endif |
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| 199 | |
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| 200 | move v0, a0 /* mem_size */ |
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| 201 | |
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| 202 | #if __mips==3 |
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| 203 | /* For MIPS 3, we need to be sure that the stack (and hence v0 |
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| 204 | * here) is aligned on a double word boundary. |
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| 205 | */ |
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| 206 | andi t0, v0, 0x7 |
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| 207 | beqz t0, 12f /* Last three bits Zero, already aligned */ |
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| 208 | nop |
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| 209 | subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ |
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| 210 | 12: |
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| 211 | #endif |
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| 212 | |
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| 213 | |
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| 214 | |
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| 215 | /************************************************************************** |
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| 216 | ** |
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| 217 | ** Permanent Stack - now know top of memory, put permanent stack there |
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| 218 | ** |
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| 219 | ***************************************************************************/ |
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| 220 | |
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| 221 | la t2, _fbss /* cache mode as linked */ |
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| 222 | and t2, 0xF0000000 /* isolate segment */ |
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| 223 | la t1, 6f |
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| 224 | j t1 /* back to original cache mode */ |
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| 225 | nop |
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| 226 | 6: |
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| 227 | or v0, t2 /* stack back to original cache mode */ |
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| 228 | addiu v0,v0,-16 /* overhead */ |
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| 229 | move sp, v0 /* now replace count w top of memory */ |
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| 230 | move v1, v0 |
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| 231 | subu v1, P_STACKSIZE /* clear requested stack size */ |
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| 232 | |
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| 233 | 7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ |
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| 234 | bltu v1,v0,7b |
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| 235 | add v1, 4 |
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| 236 | .set reorder |
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| 237 | |
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| 238 | #ifdef _R3000 |
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| 239 | jal flush_Icache |
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| 240 | jal flush_Dcache /* flush Data & Instruction caches */ |
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| 241 | #endif |
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| 242 | #ifdef _R4000 |
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| 243 | jal flush_cache_nowrite /* flush Data & Instruction caches */ |
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| 244 | #endif |
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| 245 | |
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| 246 | |
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| 247 | |
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| 248 | /************************************************************************** |
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| 249 | ** |
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| 250 | ** If this chip supports a Translation Lookaside Buffer, clear it |
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| 251 | ** |
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| 252 | ***************************************************************************/ |
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| 253 | |
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| 254 | .set noreorder |
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| 255 | mfc0 t1, C0_SR /* look at Status Register */ |
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| 256 | nop |
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| 257 | .set reorder |
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| 258 | #ifdef _R3000 |
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| 259 | li t2, SR_TS /* TLB Shutdown bit */ |
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| 260 | and t1,t2 /* TLB Shutdown if 1 */ |
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| 261 | bnez t1, 8f /* skip clearing if no TLB */ |
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| 262 | #endif |
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| 263 | |
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| 264 | #ifndef R4650 |
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| 265 | jal init_tlb /* clear the tlb */ |
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| 266 | #endif |
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| 267 | |
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| 268 | |
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| 269 | /************************************************************************ |
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| 270 | ** |
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| 271 | ** Initialization required if using IDT/c or libc.a, standard C Lib |
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| 272 | ** |
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| 273 | ** can SKIP if not necessary for application |
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| 274 | ** |
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| 275 | ************************************************************************/ |
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| 276 | 8: |
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| 277 | |
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| 278 | jal idtsim_init_sbrk |
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| 279 | jal idtsim_init_file |
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| 280 | /*********************** END I/O initialization **********************/ |
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| 281 | |
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| 282 | |
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| 283 | jal main |
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| 284 | |
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| 285 | jal idtsim_promexit |
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| 286 | |
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| 287 | ENDFRAME(start) |
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| 288 | |
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| 289 | |
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| 290 | .globl sim_mem_cfg |
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| 291 | sim_mem_cfg: |
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| 292 | .set noat |
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| 293 | .set noreorder |
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| 294 | li AT, (0xbfc00000+((55)*8)) |
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| 295 | jr AT |
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| 296 | nop |
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| 297 | .set at |
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| 298 | .set reorder |
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