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idtmem.S @ 9b4422a2

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Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

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1	/*
2
3	Based upon IDT provided code with the following release:
4
5	This source code has been made available to you by IDT on an AS-IS
6	basis. Anyone receiving this source is licensed under IDT copyrights
7	to use it in any way he or she deems fit, including copying it,
8	modifying it, compiling it, and redistributing it either with or
9	without modifications. No license under IDT patents or patent
10	applications is to be implied by the copyright license.
11
12	Any user of this software should understand that IDT cannot provide
13	technical support for this software and will not be responsible for
14	any consequences resulting from the use of this software.
15
16	Any person who transfers this source code or any derivative work must
17	include the IDT copyright notice, this paragraph, and the preceeding
18	two paragraphs in the transferred software.
19
20	COPYRIGHT IDT CORPORATION 1996
21	LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22
23	*/
24
25	/************************************************************************
26	**
27	** idtmem.s - memory and cache functions
28	**
29	** Copyright 1991 Integrated Device Technology, Inc.
30	** All Rights Reserved
31	**
32	**************************************************************************/
33
34	/*
35	* 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack
36	* to set mem_size.
37	*/
38
39	#include <rtems/mips/iregdef.h>
40	#include <rtems/mips/idtcpu.h>
41	#include <rtems/asm.h>
42
43	.data
44	mem_size:
45	.word 0
46	dcache_size:
47	.word 0
48	icache_size:
49	#if __mips == 1
50	.word MINCACHE
51	#endif
52	#if __mips == 3
53	.word 0
54	#endif
55
56	#if __mips == 3
57	.data
58	scache_size:
59	.word 0
60	icache_linesize:
61	.word 0
62	dcache_linesize:
63	.word 0
64	scache_linesize:
65	.word 0
66	#endif
67
68	.text
69
70	#if __mips == 1
71	#define CONFIGFRM ((2*4)+4)
72
73	/*************************************************************************
74	**
75	** Config_Dcache() -- determine size of Data cache
76	**
77	**************************************************************************/
78
79	FRAME(config_Dcache,sp, CONFIGFRM, ra)
80	.set noreorder
81	subu sp,CONFIGFRM
82	sw ra,CONFIGFRM-4(sp) /* save return address */
83	sw s0,44(sp) / save s0 in first regsave slot */
84	mfc0 s0,C0_SR /* save SR */
85	nop
86	mtc0 zero,C0_SR /* disable interrupts */
87	.set reorder
88	jal _size_cache /* returns Data cache size in v0 */
89	sw v0, dcache_size /* save it */
90	and s0, ~SR_PE /* do not clear PE */
91	.set noreorder
92	mtc0 s0,C0_SR /* restore SR */
93	nop
94	.set reorder
95	lw s0, 44(sp) / restore s0 */
96	lw ra,CONFIGFRM-4(sp) /* restore ra */
97	addu sp,CONFIGFRM /* pop stack */
98	j ra
99	ENDFRAME(config_Dcache)
100
101	/*************************************************************************
102	**
103	** Config_Icache() -- determine size of Instruction cache
104	** MUST be run in uncached mode/handled in idt_csu.s
105	**
106	**************************************************************************/
107
108	FRAME(config_Icache,sp, CONFIGFRM, ra)
109	.set noreorder
110	subu sp,CONFIGFRM
111	sw ra,CONFIGFRM-4(sp) /* save return address */
112	sw s0,44(sp) / save s0 in first regsave slot */
113	mfc0 s0,C0_SR /* save SR */
114	nop
115	mtc0 zero, C0_SR /* disable interrupts */
116	li v0,SR_SWC /* swap caches/disable ints */
117	mtc0 v0,C0_SR
118	nop
119	.set reorder
120	jal _size_cache /* returns instruction cache size */
121	.set noreorder
122	mtc0 zero,C0_SR /* swap back caches */
123	nop
124	and s0,~SR_PE /* do not inadvertantly clear PE */
125	mtc0 s0,C0_SR /* restore SR */
126	nop
127	.set reorder
128	sw v0, icache_size /* save it AFTER caches back */
129	lw s0,44(sp) / restore s0 */
130	lw ra,CONFIGFRM-4(sp) /* restore ra */
131	addu sp,CONFIGFRM /* pop stack */
132	j ra
133	ENDFRAME(config_Icache)
134
135	/************************************************************************
136	**
137	** _size_cache()
138	** returns cache size in v0
139	**
140	************************************************************************/
141
142	FRAME(_size_cache,sp,0,ra)
143	.set noreorder
144	mfc0 t0,C0_SR /* save current sr */
145	nop
146	and t0,~SR_PE /* do not inadvertently clear PE */
147	or v0,t0,SR_ISC /* isolate cache */
148	mtc0 v0,C0_SR
149	/*
150	* First check if there is a cache there at all
151	*/
152	move v0,zero
153	li v1,0xa5a5a5a5 /* distinctive pattern */
154	sw v1,K0BASE /* try to write into cache */
155	lw t1,K0BASE /* try to read from cache */
156	nop
157	mfc0 t2,C0_SR
158	nop
159	.set reorder
160	and t2,SR_CM
161	bne t2,zero,3f /* cache miss, must be no cache */
162	bne v1,t1,3f /* data not equal -> no cache */
163	/*
164	* Clear cache size boundries to known state.
165	*/
166	li v0,MINCACHE
167	1:
168	sw zero,K0BASE(v0)
169	sll v0,1
170	ble v0,MAXCACHE,1b
171
172	li v0,-1
173	sw v0,K0BASE(zero) /* store marker in cache */
174	li v0,MINCACHE /* MIN cache size */
175
176	2: lw v1,K0BASE(v0) /* Look for marker */
177	bne v1,zero,3f /* found marker */
178	sll v0,1 /* cache size * 2 */
179	ble v0,MAXCACHE,2b /* keep looking */
180	move v0,zero /* must be no cache */
181	.set noreorder
182	3: mtc0 t0,C0_SR /* restore sr */
183	j ra
184	nop
185	ENDFRAME(_size_cache)
186	.set reorder
187
188	#define FLUSHFRM (2*4)
189
190	/***************************************************************************
191	**
192	** flush_Dcache() - flush entire Data cache
193	**
194	****************************************************************************/
195	FRAME(flush_Dcache,sp,FLUSHFRM,ra)
196	lw t2, dcache_size
197	.set noreorder
198	mfc0 t3,C0_SR /* save SR */
199	nop
200	and t3,~SR_PE /* dont inadvertently clear PE */
201	beq t2,zero,_Dflush_done /* no D cache, get out! */
202	nop
203	li v0, SR_ISC /* isolate cache */
204	mtc0 v0, C0_SR
205	nop
206	.set reorder
207	li t0,K0BASE /* set loop registers */
208	or t1,t0,t2
209
210	2: sb zero,0(t0)
211	sb zero,4(t0)
212	sb zero,8(t0)
213	sb zero,12(t0)
214	sb zero,16(t0)
215	sb zero,20(t0)
216	sb zero,24(t0)
217	addu t0,32
218	sb zero,-4(t0)
219	bne t0,t1,2b
220
221	.set noreorder
222	_Dflush_done:
223	mtc0 t3,C0_SR /* restore Status Register */
224	.set reorder
225	j ra
226	ENDFRAME(flush_Dcache)
227
228	/***************************************************************************
229	**
230	** flush_Icache() - flush entire Instruction cache
231	**
232	** NOTE: Icache can only be flushed/cleared when uncached
233	** Code forces into uncached memory regardless of calling mode
234	**
235	****************************************************************************/
236	FRAME(flush_Icache,sp,FLUSHFRM,ra)
237	lw t1,icache_size
238	.set noreorder
239	mfc0 t3,C0_SR /* save SR */
240	nop
241	la v0,1f
242	li v1,K1BASE
243	or v0,v1
244	j v0 /* force into non-cached space */
245	nop
246	1:
247	and t3,~SR_PE /* dont inadvertently clear PE */
248	beq t1,zero,_Iflush_done /* no i-cache get out */
249	nop
250	li v0,SR_ISC\|SR_SWC /* disable intr, isolate and swap */
251	mtc0 v0,C0_SR
252	li t0,K0BASE
253	.set reorder
254	or t1,t0,t1
255
256	1: sb zero,0(t0)
257	sb zero,4(t0)
258	sb zero,8(t0)
259	sb zero,12(t0)
260	sb zero,16(t0)
261	sb zero,20(t0)
262	sb zero,24(t0)
263	addu t0,32
264	sb zero,-4(t0)
265	bne t0,t1,1b
266	.set noreorder
267	_Iflush_done:
268	mtc0 t3,C0_SR /* un-isolate, enable interrupts */
269	.set reorder
270	j ra
271	ENDFRAME(flush_Icache)
272
273	/**************************************************************************
274	**
275	** clear_Dcache(base_addr, byte_count) - flush portion of Data cache
276	**
277	** a0 = base address of portion to be cleared
278	** a1 = byte count of length
279	**
280	***************************************************************************/
281	FRAME(clear_Dcache,sp,0,ra)
282
283	lw t2, dcache_size /* Data cache size */
284	.set noreorder
285	mfc0 t3,C0_SR /* save SR */
286	nop
287	and t3,~SR_PE /* dont inadvertently clear PE */
288	nop
289	nop
290	.set reorder
291	/*
292	* flush data cache
293	*/
294
295	.set noreorder
296	nop
297	li v0,SR_ISC /* isolate data cache */
298	mtc0 v0,C0_SR
299	.set reorder
300	bltu t2,a1,1f /* cache is smaller than region */
301	move t2,a1
302	1: addu t2,a0 /* ending address + 1 */
303	move t0,a0
304
305	1: sb zero,0(t0)
306	sb zero,4(t0)
307	sb zero,8(t0)
308	sb zero,12(t0)
309	sb zero,16(t0)
310	sb zero,20(t0)
311	sb zero,24(t0)
312	addu t0,32
313	sb zero,-4(t0)
314	bltu t0,t2,1b
315
316	.set noreorder
317	mtc0 t3,C0_SR /* un-isolate, enable interrupts */
318	nop
319	.set reorder
320	j ra
321	ENDFRAME(clear_Dcache)
322
323	/**************************************************************************
324	**
325	** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache
326	**
327	** a0 = base address of portion to be cleared
328	** a1 = byte count of length
329	**
330	** NOTE: Icache can only be flushed/cleared when uncached
331	** Code forces into uncached memory regardless of calling mode
332	**
333	***************************************************************************/
334	FRAME(clear_Icache,sp,0,ra)
335
336	lw t1, icache_size /* Instruction cache size */
337	/*
338	* flush text cache
339	*/
340	.set noreorder
341	mfc0 t3,C0_SR /* save SR */
342	nop
343	la v0,1f
344	li v1,K1BASE
345	or v0,v1
346	j v0 /* force into non-cached space */
347	nop
348	1:
349	and t3,~SR_PE /* dont inadvertently clear PE */
350	nop
351	nop
352	li v0,SR_ISC\|SR_SWC /* disable intr, isolate and swap */
353	mtc0 v0,C0_SR
354	.set reorder
355	bltu t1,a1,1f /* cache is smaller than region */
356	move t1,a1
357	1: addu t1,a0 /* ending address + 1 */
358	move t0,a0
359
360	sb zero,0(t0)
361	sb zero,4(t0)
362	sb zero,8(t0)
363	sb zero,12(t0)
364	sb zero,16(t0)
365	sb zero,20(t0)
366	sb zero,24(t0)
367	addu t0,32
368	sb zero,-4(t0)
369	bltu t0,t1,1b
370	.set noreorder
371	mtc0 t3,C0_SR /* un-isolate, enable interrupts */
372	nop
373	nop
374	nop /* allow time for caches to swap */
375	.set reorder
376	j ra
377	ENDFRAME(clear_Icache)
378
379	/**************************************************************************
380	**
381	** get_mem_conf - get memory configuration
382	**
383	***************************************************************************/
384
385	FRAME(get_mem_conf,sp,0,ra)
386
387	lw t6, mem_size
388	sw t6, 0(a0)
389	lw t7, icache_size
390	sw t7, 4(a0)
391	lw t8, dcache_size
392	sw t8, 8(a0)
393	j ra
394
395	ENDFRAME(get_mem_conf)
396	#endif /* __mips == 1 */
397
398	#if __mips == 3
399	#define LEAF(label) FRAME(label,sp,0,ra)
400	#define XLEAF(label) \
401	.globl label ; \
402	label:
403
404	/*
405	* cacheop macro to automate cache operations
406	* first some helpers...
407	*/
408	#define _mincache(size, maxsize) \
409	bltu size,maxsize,8f ; \
410	move size,maxsize ; \
411	8:
412
413	#define _align(tmp, minaddr, maxaddr, linesize) \
414	subu tmp,linesize,1 ; \
415	not tmp ; \
416	and minaddr,tmp ; \
417	addu maxaddr,-1 ; \
418	and maxaddr,tmp
419
420	/* This is a bit of a hack really because it relies on minaddr=a0 */
421	#define _doop1(op1) \
422	cache op1,0(a0)
423
424	#define _doop2(op1, op2) \
425	cache op1,0(a0) ; \
426	cache op2,0(a0)
427
428	/* specials for cache initialisation */
429	#define _doop1lw1(op1) \
430	cache op1,0(a0) ; \
431	lw zero,0(a0) ; \
432	cache op1,0(a0)
433
434	#define _doop121(op1,op2) \
435	cache op1,0(a0) ; \
436	nop; \
437	cache op2,0(a0) ; \
438	nop; \
439	cache op1,0(a0)
440
441	#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
442	.set noreorder ; \
443	7: _doop##tag##ops ; \
444	bne minaddr,maxaddr,7b ; \
445	addu minaddr,linesize ; \
446	.set reorder
447
448	/* finally the cache operation macros */
449	#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
450	_mincache(n, cache_size); \
451	blez n,9f ; \
452	addu n,kva ; \
453	_align(t1, kva, n, cache_linesize) ; \
454	_oploopn(kva, n, cache_linesize, tag, ops) ; \
455	9:
456
457	#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
458	blez n,9f ; \
459	addu n,kva ; \
460	_align(t1, kva, n, cache_linesize) ; \
461	_oploopn(kva, n, cache_linesize, tag, ops) ; \
462	9:
463
464	#define icacheop(kva, n, cache_size, cache_linesize, op) \
465	icacheopn(kva, n, cache_size, cache_linesize, 1, (op))
466
467	#define vcacheop(kva, n, cache_size, cache_linesize, op) \
468	vcacheopn(kva, n, cache_size, cache_linesize, 1, (op))
469
470	.text
471
472	/*
473	* static void _size_cache() R4000
474	*
475	* Internal routine to determine cache sizes by looking at R4000 config
476	* register. Sizes are returned in registers, as follows:
477	* t2 icache size
478	* t3 dcache size
479	* t6 scache size
480	* t4 icache line size
481	* t5 dcache line size
482	* t7 scache line size
483	*/
484	LEAF(_size_cache)
485	mfc0 t0,C0_CONFIG
486
487	and t1,t0,CFG_ICMASK
488	srl t1,CFG_ICSHIFT
489	li t2,0x1000
490	sll t2,t1
491
492	and t1,t0,CFG_DCMASK
493	srl t1,CFG_DCSHIFT
494	li t3,0x1000
495	sll t3,t1
496
497	li t4,32
498	and t1,t0,CFG_IB
499	bnez t1,1f
500	li t4,16
501	1:
502
503	li t5,32
504	and t1,t0,CFG_DB
505	bnez t1,1f
506	li t5,16
507	1:
508
509	move t6,zero # default to no scache
510	move t7,zero #
511
512	and t1,t0,CFG_C_UNCACHED # test config register
513	bnez t1,1f # no scache if uncached/non-coherent
514
515	li t6,0x100000 # assume 1Mb scache <<-NOTE
516	and t1,t0,CFG_SBMASK
517	srl t1,CFG_SBSHIFT
518	li t7,16
519	sll t7,t1
520	1: j ra
521	ENDFRAME(_size_cache)
522
523	/*
524	* void config_cache() R4000
525	*
526	* Work out size of I, D & S caches, assuming they are already initialised.
527	*/
528	LEAF(config_cache)
529	lw t0,icache_size
530	bgtz t0,8f # already known?
531	move v0,ra
532	bal _size_cache
533	move ra,v0
534
535	sw t2,icache_size
536	sw t3,dcache_size
537	sw t6,scache_size
538	sw t4,icache_linesize
539	sw t5,dcache_linesize
540	sw t7,scache_linesize
541	8: j ra
542	ENDFRAME(config_cache)
543
544	/*
545	* void _init_cache() R4000
546	*/
547	LEAF(_init_cache)
548	/*
549	* First work out the sizes
550	*/
551	move v0,ra
552	bal _size_cache
553	move ra,v0
554
555	/*
556	* The caches may be in an indeterminate state,
557	* so we force good parity into them by doing an
558	* invalidate, load/fill, invalidate for each line.
559	*/
560
561	/* disable all i/u and cache exceptions */
562	mfc0 v0,C0_SR
563	and v1,v0,~SR_IE
564	or v1,SR_DE
565	mtc0 v1,C0_SR
566
567	mtc0 zero,C0_TAGLO
568	mtc0 zero,C0_TAGHI
569
570	/* assume bottom of RAM will generate good parity for the cache */
571	li a0,PHYS_TO_K0(0)
572	move a2,t2 # icache_size
573	move a3,t4 # icache_linesize
574	move a1,a2
575	icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I))
576
577	li a0,PHYS_TO_K0(0)
578	move a2,t3 # dcache_size
579	move a3,t5 # dcache_linesize
580	move a1,a2
581	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D))
582
583	/* assume unified I & D in scache <<-NOTE */
584	blez t6,1f
585	li a0,PHYS_TO_K0(0)
586	move a2,t6
587	move a3,t7
588	move a1,a2
589	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD))
590
591	1: mtc0 v0,C0_SR
592	j ra
593	ENDFRAME(_init_cache)
594
595	/*
596	* void flush_cache (void) R4000
597	*
598	* Flush and invalidate all caches
599	*/
600	LEAF(flush_cache)
601	/* secondary cacheops do all the work if present */
602	lw a2,scache_size
603	blez a2,1f
604	lw a3,scache_linesize
605	li a0,PHYS_TO_K0(0)
606	move a1,a2
607	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
608	b 2f
609
610	1:
611	lw a2,icache_size
612	blez a2,2f
613	lw a3,icache_linesize
614	li a0,PHYS_TO_K0(0)
615	move a1,a2
616	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
617
618	lw a2,dcache_size
619	lw a3,dcache_linesize
620	li a0,PHYS_TO_K0(0)
621	move a1,a2
622	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
623
624	2: j ra
625	ENDFRAME(flush_cache)
626
627	/*
628	* void flush_cache_nowrite (void) R4000
629	*
630	* Invalidate all caches
631	*/
632	LEAF(flush_cache_nowrite)
633	mfc0 v0,C0_SR
634	and v1,v0,~SR_IE
635	mtc0 v1,C0_SR
636
637	mtc0 zero,C0_TAGLO
638	mtc0 zero,C0_TAGHI
639
640	lw a2,icache_size
641	blez a2,2f
642	lw a3,icache_linesize
643	li a0,PHYS_TO_K0(0)
644	move a1,a2
645	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
646
647	lw a2,dcache_size
648	lw a3,dcache_linesize
649	li a0,PHYS_TO_K0(0)
650	move a1,a2
651	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
652
653	lw a2,scache_size
654	blez a2,2f
655	lw a3,scache_linesize
656	li a0,PHYS_TO_K0(0)
657	move a1,a2
658	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
659
660	2: mtc0 v0,C0_SR
661	j ra
662	ENDFRAME(flush_cache_nowrite)
663
664	/*
665	* void clean_cache (unsigned kva, size_t n) R4000
666	*
667	* Writeback and invalidate address range in all caches
668	*/
669	LEAF(clean_cache)
670	XLEAF(clear_cache)
671
672	/* secondary cacheops do all the work (if fitted) */
673	lw a2,scache_size
674	blez a2,1f
675	lw a3,scache_linesize
676	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
677	b 2f
678
679	1: lw a2,icache_size
680	blez a2,2f
681	lw a3,icache_linesize
682	/* save kva & n for subsequent loop */
683	move t8,a0
684	move t9,a1
685	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
686
687	lw a2,dcache_size
688	lw a3,dcache_linesize
689	/* restore kva & n */
690	move a0,t8
691	move a1,t9
692	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
693
694	2: j ra
695	ENDFRAME(clean_cache)
696
697	/*
698	* void clean_dcache (unsigned kva, size_t n) R4000
699	*
700	* Writeback and invalidate address range in primary data cache
701	*/
702	LEAF(clean_dcache)
703	lw a2,dcache_size
704	blez a2,2f
705	lw a3,dcache_linesize
706
707	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
708
709	2: j ra
710	ENDFRAME(clean_dcache)
711
712	/*
713	* void clean_dcache_indexed (unsigned kva, size_t n) R4000
714	*
715	* Writeback and invalidate indexed range in primary data cache
716	*/
717	LEAF(clean_dcache_indexed)
718	lw a2,dcache_size
719	blez a2,2f
720	lw a3,dcache_linesize
721
722	#ifdef CPU_ORION
723	srl a2,1 # do one set (half cache) at a time
724	move t8,a0 # save kva & n
725	move t9,a1
726	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
727
728	addu a0,t8,a2 # do next set
729	move a1,t9 # restore n
730	#endif
731	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
732
733	2: j ra
734	ENDFRAME(clean_dcache_indexed)
735
736	/*
737	* void clean_dcache_nowrite (unsigned kva, size_t n) R4000
738	*
739	* Invalidate an address range in primary data cache
740	*/
741	LEAF(clean_dcache_nowrite)
742	lw a2,dcache_size
743	blez a2,2f
744	lw a3,dcache_linesize
745
746	vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
747
748	2: j ra
749	ENDFRAME(clean_dcache_nowrite)
750
751	/*
752	* void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000
753	*
754	* Invalidate indexed range in primary data cache
755	*/
756	LEAF(clean_dcache_nowrite_indexed)
757	mfc0 v0,C0_SR
758	and v1,v0,~SR_IE
759	mtc0 v1,C0_SR
760
761	mtc0 zero,C0_TAGLO
762	mtc0 zero,C0_TAGHI
763
764	lw a2,dcache_size
765	blez a2,2f
766	lw a3,dcache_linesize
767
768	#ifdef CPU_ORION
769	srl a2,1 # do one set (half cache) at a time
770	move t8,a0 # save kva & n
771	move t9,a1
772	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
773
774	addu a0,t8,a2 # do next set
775	move a1,t9 # restore n
776	#endif
777	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
778
779	2: mtc0 v0,C0_SR
780	j ra
781	ENDFRAME(clean_dcache_nowrite_indexed)
782
783	/*
784	* void clean_icache (unsigned kva, size_t n) R4000
785	*
786	* Invalidate address range in primary instruction cache
787	*/
788	LEAF(clean_icache)
789	lw a2,icache_size
790	blez a2,2f
791	lw a3,icache_linesize
792
793	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
794
795	2: j ra
796	ENDFRAME(clean_icache)
797
798	/*
799	* void clean_icache_indexed (unsigned kva, size_t n) R4000
800	*
801	* Invalidate indexed range in primary instruction cache
802	*/
803	LEAF(clean_icache_indexed)
804	lw a2,icache_size
805	blez a2,2f
806	lw a3,icache_linesize
807
808	#ifdef CPU_ORION
809	srl a2,1 # do one set (half cache) at a time
810	move t8,a0 # save kva & n
811	move t9,a1
812	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
813
814	addu a0,t8,a2 # do next set
815	move a1,t9 # restore n
816	#endif
817	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
818
819	2: j ra
820	ENDFRAME(clean_icache_indexed)
821
822	/*
823	* void clean_scache (unsigned kva, size_t n) R4000
824	*
825	* Writeback and invalidate address range in secondary cache
826	*/
827	LEAF(clean_scache)
828	lw a2,scache_size
829	blez a2,2f
830	lw a3,scache_linesize
831	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
832
833	2: j ra
834	ENDFRAME(clean_scache)
835
836	/*
837	* void clean_scache_indexed (unsigned kva, size_t n) R4000
838	*
839	* Writeback and invalidate indexed range in secondary cache
840	*/
841	LEAF(clean_scache_indexed)
842	lw a2,scache_size
843	blez a2,2f
844	lw a3,scache_linesize
845
846	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
847
848	2: j ra
849	ENDFRAME(clean_scache_indexed)
850
851	/*
852	* void clean_scache_nowrite (unsigned kva, size_t n) R4000
853	*
854	* Invalidate an address range in secondary cache
855	*/
856	LEAF(clean_scache_nowrite)
857	lw a2,scache_size
858	blez a2,2f
859	lw a3,scache_linesize
860
861	vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)
862
863	2: j ra
864	ENDFRAME(clean_scache_nowrite)
865
866	/*
867	* void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000
868	*
869	* Invalidate indexed range in secondary cache
870	*/
871	LEAF(clean_scache_nowrite_indexed)
872	mfc0 v0,C0_SR
873	and v1,v0,~SR_IE
874	mtc0 v1,C0_SR
875
876	mtc0 zero,C0_TAGLO
877	mtc0 zero,C0_TAGHI
878
879	lw a2,scache_size
880	blez a2,2f
881	lw a3,scache_linesize
882
883	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
884
885	2: mtc0 v0,C0_SR
886	j ra
887	ENDFRAME(clean_scache_nowrite_indexed)
888
889	/**************************************************************************
890	**
891	** get_mem_conf - get memory configuration R4000
892	**
893	***************************************************************************/
894
895	FRAME(get_mem_conf,sp,0,ra)
896
897	lw t6, mem_size
898	sw t6, 0(a0)
899	lw t7, icache_size
900	sw t7, 4(a0)
901	lw t8, dcache_size
902	sw t8, 8(a0)
903	lw t7, scache_size
904	sw t7, 12(a0)
905	j ra
906
907	ENDFRAME(get_mem_conf)
908
909	#endif /* __mips == 3 */
910
911	/*
912	* void set_mem_size (mem_size)
913	*
914	* config_memory()'s memory size gets written into mem_size here.
915	* Now we don't need to call config_cache() with memory size - New to IDTC6.0
916	*/
917	FRAME(set_memory_size,sp,0,ra)
918	sw a0, mem_size
919	j ra
920	ENDFRAME(set_memory_size)

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