1 | /** |
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2 | * @file |
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3 | * @ingroup mips_regs |
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4 | * @brief Standard MIPS register names. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * regs.S -- standard MIPS register names. |
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9 | * |
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10 | * Copyright (c) 1995 Cygnus Support |
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11 | * |
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12 | * The authors hereby grant permission to use, copy, modify, distribute, |
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13 | * and license this software and its documentation for any purpose, provided |
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14 | * that existing copyright notices are retained in all copies and that this |
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15 | * notice is included verbatim in any distributions. No written agreement, |
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16 | * license, or royalty fee is required for any of the authorized uses. |
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17 | * Modifications to this software may be copyrighted by their authors |
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18 | * and need not follow the licensing terms described here, provided that |
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19 | * the new terms are clearly indicated on the first page of each file where |
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20 | * they apply. |
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21 | */ |
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22 | |
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23 | /** |
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24 | * @defgroup mips_regs MIPS Registers |
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25 | * @ingroup mips_shared |
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26 | * @brief MIPS Registers |
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27 | * @{ |
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28 | */ |
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29 | |
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30 | /** |
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31 | * @name Standard MIPS register names: |
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32 | * @{ |
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33 | */ |
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34 | |
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35 | #define zero $0 |
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36 | #define z0 $0 |
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37 | #define v0 $2 |
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38 | #define v1 $3 |
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39 | #define a0 $4 |
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40 | #define a1 $5 |
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41 | #define a2 $6 |
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42 | #define a3 $7 |
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43 | #define t0 $8 |
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44 | #define t1 $9 |
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45 | #define t2 $10 |
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46 | #define t3 $11 |
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47 | #define t4 $12 |
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48 | #define t5 $13 |
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49 | #define t6 $14 |
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50 | #define t7 $15 |
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51 | #define s0 $16 |
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52 | #define s1 $17 |
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53 | #define s2 $18 |
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54 | #define s3 $19 |
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55 | #define s4 $20 |
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56 | #define s5 $21 |
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57 | #define s6 $22 |
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58 | #define s7 $23 |
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59 | #define t8 $24 |
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60 | #define t9 $25 |
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61 | #define k0 $26 ///< @brief kernel private register 0 */ |
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62 | #define k1 $27 ///< @brief kernel private register 1 */ |
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63 | #define gp $28 ///< @brief global data pointer */ |
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64 | #define sp $29 ///< @brief stack-pointer */ |
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65 | #define fp $30 ///< @brief frame-pointer */ |
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66 | #define ra $31 ///< @brief return address */ |
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67 | #define pc $pc ///< @brief pc, used on mips16 */ |
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68 | |
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69 | #define fp0 $f0 |
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70 | #define fp1 $f1 |
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71 | |
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72 | /** @} */ |
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73 | |
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74 | /** |
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75 | * @name Useful memory constants: |
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76 | * @{ |
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77 | */ |
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78 | |
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79 | #define K0BASE 0x80000000 |
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80 | #ifndef __mips64 |
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81 | #define K1BASE 0xA0000000 |
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82 | #else |
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83 | #define K1BASE 0xFFFFFFFFA0000000LL |
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84 | #endif |
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85 | |
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86 | /** @} */ |
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87 | |
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88 | #define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) |
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89 | |
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90 | /** |
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91 | * @name Standard Co-Processor 0 register numbers: |
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92 | * @{ |
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93 | */ |
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94 | |
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95 | #define C0_COUNT $9 ///< @brief Count Register */ |
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96 | #define C0_SR $12 ///< @brief Status Register */ |
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97 | #define C0_CAUSE $13 ///< @brief last exception description */ |
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98 | #define C0_EPC $14 ///< @brief Exception error address */ |
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99 | #define C0_CONFIG $16 ///< @brief CPU configuration */ |
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100 | |
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101 | /** @} */ |
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102 | |
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103 | /** |
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104 | * @name Standard Status Register bitmasks: |
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105 | * @{ |
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106 | */ |
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107 | |
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108 | #define SR_CU1 0x20000000 ///< @brief Mark CP1 as usable */ |
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109 | #define SR_FR 0x04000000 ///< @brief Enable MIPS III FP registers */ |
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110 | #define SR_BEV 0x00400000 ///< @brief Controls location of exception vectors */ |
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111 | #define SR_PE 0x00100000 ///< @brief Mark soft reset (clear parity error) */ |
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112 | |
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113 | #define SR_KX 0x00000080 ///< @brief Kernel extended addressing enabled */ |
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114 | #define SR_SX 0x00000040 ///< @brief Supervisor extended addressing enabled */ |
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115 | #define SR_UX 0x00000020 ///< @brief User extended addressing enabled */ |
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116 | |
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117 | /** @} */ |
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118 | |
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119 | /** |
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120 | * @name Standard (R4000) cache operations. |
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121 | * @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition: |
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122 | * @{ |
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123 | */ |
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124 | |
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125 | #define CACHE_I (0) ///< @brief primary instruction */ |
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126 | #define CACHE_D (1) ///< @brief primary data */ |
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127 | #define CACHE_SI (2) ///< @brief secondary instruction */ |
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128 | #define CACHE_SD (3) ///< @brief secondary data (or combined instruction/data) */ |
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129 | |
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130 | #define INDEX_INVALIDATE (0) ///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */ |
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131 | #define INDEX_LOAD_TAG (1) |
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132 | #define INDEX_STORE_TAG (2) |
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133 | #define CREATE_DIRTY_EXCLUSIVE (3) ///< @brief CACHE_D and CACHE_SD only */ |
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134 | #define HIT_INVALIDATE (4) |
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135 | #define CACHE_FILL (5) ///< @brief CACHE_I only */ |
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136 | #define HIT_WRITEBACK_INVALIDATE (5) ///< @brief CACHE_D and CACHE_SD only */ |
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137 | #define HIT_WRITEBACK (6) ///< @brief CACHE_I, CACHE_D and CACHE_SD only */ |
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138 | #define HIT_SET_VIRTUAL (7) ///< @brief CACHE_SI and CACHE_SD only */ |
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139 | |
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140 | #define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) |
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141 | |
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142 | /** @} */ |
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143 | |
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144 | /** |
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145 | * @name Individual cache operations: |
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146 | * @{ |
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147 | */ |
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148 | |
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149 | #define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) |
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150 | #define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) |
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151 | #define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) |
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152 | #define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) |
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153 | |
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154 | #define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) |
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155 | #define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) |
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156 | #define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) |
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157 | #define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) |
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158 | |
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159 | #define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) |
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160 | #define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) |
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161 | #define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) |
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162 | #define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) |
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163 | |
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164 | #define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) |
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165 | #define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) |
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166 | |
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167 | #define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) |
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168 | #define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) |
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169 | #define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) |
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170 | #define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) |
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171 | |
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172 | #define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) |
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173 | #define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) |
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174 | #define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) |
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175 | |
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176 | #define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) |
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177 | #define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) |
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178 | #define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) |
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179 | |
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180 | #define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) |
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181 | #define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) |
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182 | |
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183 | /** @} */ |
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184 | |
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185 | /** @} */ |
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186 | |
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187 | /*> EOF regs.S <*/ |
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