1 | /** |
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2 | * @file |
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3 | * @ingroup mips_i8259_irq |
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4 | * @brief Data structure and functions used to control i8259 chip. |
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5 | */ |
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6 | |
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7 | /* irq.h |
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8 | * |
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9 | * This include file describe the data structure and the functions implemented |
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10 | * by RTEMS to control the i8259 chip. |
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11 | * |
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12 | * Copyright (C) 1999 valette@crf.canon.fr |
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13 | * |
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14 | * This code is heavilly inspired by the public specification of STREAM V2 |
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15 | * that can be found at : |
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16 | * |
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17 | * <http://www.chorus.com/Documentation/index.html> by following |
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18 | * the STREAM API Specification Document link. |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.com/license/LICENSE. |
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23 | */ |
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24 | |
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25 | #ifndef I8259_H |
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26 | #define I8259_H |
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27 | |
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28 | /** |
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29 | * @defgroup mips_i8259_irq i8259 Chip Support |
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30 | * @ingroup mips_shared |
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31 | * @brief i8259 Chip Support |
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32 | * @{ |
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33 | */ |
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34 | |
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35 | /** |
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36 | * @name 8259 edge/level control definitions at VIA |
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37 | * @{ |
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38 | */ |
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39 | |
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40 | #if 1 |
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41 | #define ISA8259_M_ELCR 0x4d0 |
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42 | #define ISA8259_S_ELCR 0x4d1 |
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43 | #endif |
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44 | |
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45 | #define ELCRS_INT15_LVL 0x80 |
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46 | #define ELCRS_INT14_LVL 0x40 |
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47 | #define ELCRS_INT13_LVL 0x20 |
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48 | #define ELCRS_INT12_LVL 0x10 |
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49 | #define ELCRS_INT11_LVL 0x08 |
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50 | #define ELCRS_INT10_LVL 0x04 |
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51 | #define ELCRS_INT9_LVL 0x02 |
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52 | #define ELCRS_INT8_LVL 0x01 |
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53 | #define ELCRM_INT7_LVL 0x80 |
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54 | #define ELCRM_INT6_LVL 0x40 |
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55 | #define ELCRM_INT5_LVL 0x20 |
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56 | #define ELCRM_INT4_LVL 0x10 |
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57 | #define ELCRM_INT3_LVL 0x8 |
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58 | #define ELCRM_INT2_LVL 0x4 |
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59 | #define ELCRM_INT1_LVL 0x2 |
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60 | #define ELCRM_INT0_LVL 0x1 |
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61 | |
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62 | /** @} */ |
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63 | |
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64 | /** |
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65 | * @name PIC's command and mask registers |
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66 | * @{ |
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67 | */ |
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68 | |
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69 | #define PIC_MASTER_COMMAND_IO_PORT 0x20 ///< @brief Master PIC command register */ |
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70 | #define PIC_SLAVE_COMMAND_IO_PORT 0xa0 ///< @brief Slave PIC command register */ |
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71 | #define PIC_MASTER_IMR_IO_PORT 0x21 ///< @brief Master PIC Interrupt Mask Register */ |
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72 | #define PIC_SLAVE_IMR_IO_PORT 0xa1 ///< @brief Slave PIC Interrupt Mask Register */ |
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73 | |
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74 | /** @} */ |
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75 | |
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76 | /** |
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77 | * @name Command for specific EOI (End Of Interrupt): Interrupt acknowledge |
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78 | * @{ |
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79 | */ |
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80 | |
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81 | #define PIC_EOSI 0x60 ///< @brief End of Specific Interrupt (EOSI) */ |
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82 | #define SLAVE_PIC_EOSI 0x62 ///< @brief End of Specific Interrupt (EOSI) for cascade */ |
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83 | #define PIC_EOI 0x20 ///< @brief Generic End of Interrupt (EOI) */ |
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84 | |
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85 | /** @} */ |
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86 | |
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87 | #ifndef ASM |
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88 | |
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89 | #ifdef __cplusplus |
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90 | extern "C" { |
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91 | #endif |
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92 | |
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93 | /* |
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94 | * rtems_irq_number Definitions |
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95 | */ |
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96 | #if 0 |
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97 | |
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98 | /** |
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99 | * @name ISA IRQ handler related definitions |
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100 | * @{ |
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101 | */ |
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102 | |
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103 | #define BSP_ISA_IRQ_NUMBER (16) |
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104 | #define BSP_ISA_IRQ_LOWEST_OFFSET (0) |
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105 | #define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) |
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106 | |
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107 | /** @} */ |
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108 | |
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109 | #ifndef qemu |
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110 | #define BSP_PCI_IRQ_NUMBER (16) |
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111 | #else |
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112 | #define BSP_PCI_IRQ_NUMBER (0) |
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113 | #endif |
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114 | #define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) |
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115 | #define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) |
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116 | |
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117 | /* |
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118 | * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt |
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119 | * handler might be connected |
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120 | */ |
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121 | #define BSP_PROCESSOR_IRQ_NUMBER (1) |
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122 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) |
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123 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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124 | /* Misc vectors for OPENPIC irqs (IPI, timers) |
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125 | */ |
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126 | #ifndef qemu |
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127 | #define BSP_MISC_IRQ_NUMBER (8) |
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128 | #else |
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129 | #define BSP_MISC_IRQ_NUMBER (0) |
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130 | #endif |
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131 | |
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132 | #define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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133 | #define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) |
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134 | |
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135 | /** |
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136 | * @name Summary |
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137 | * @{ |
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138 | */ |
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139 | |
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140 | #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) |
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141 | #define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) |
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142 | #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) |
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143 | |
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144 | /** @} */ |
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145 | |
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146 | /** |
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147 | * @name Some ISA IRQ symbolic name definition |
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148 | * @{ |
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149 | */ |
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150 | |
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151 | #define BSP_ISA_PERIODIC_TIMER (0) |
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152 | #define BSP_ISA_KEYBOARD (1) |
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153 | #define BSP_ISA_UART_COM2_IRQ (3) |
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154 | #define BSP_ISA_UART_COM1_IRQ (4) |
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155 | #define BSP_ISA_RT_TIMER1 (8) |
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156 | #define BSP_ISA_RT_TIMER3 (10) |
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157 | |
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158 | /** @} */ |
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159 | |
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160 | /** |
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161 | * @name Some PCI IRQ symbolic name definition |
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162 | * @{ |
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163 | */ |
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164 | |
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165 | #define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) |
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166 | #if BSP_PCI_IRQ_NUMBER > 0 |
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167 | #define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0) |
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168 | #endif |
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169 | |
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170 | /** @} */ |
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171 | |
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172 | #if defined(mvme2100) |
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173 | #define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) |
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174 | #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) |
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175 | #define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) |
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176 | #define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4) |
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177 | #define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5) |
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178 | #define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7) |
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179 | #define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) |
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180 | #define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) |
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181 | #define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) |
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182 | #define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13) |
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183 | #define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14) |
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184 | #define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15) |
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185 | #else |
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186 | #define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ |
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187 | #define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ |
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188 | #endif |
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189 | |
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190 | /** |
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191 | * @brief Some Processor execption handled as RTEMS IRQ symbolic name definition |
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192 | */ |
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193 | #define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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194 | #endif |
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195 | |
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196 | /** |
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197 | * @name Type definition for RTEMS managed interrupts |
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198 | * @{ |
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199 | */ |
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200 | |
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201 | typedef unsigned short rtems_i8259_masks; |
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202 | extern volatile rtems_i8259_masks i8259s_cache; |
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203 | |
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204 | /** @} */ |
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205 | |
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206 | /*-------------------------------------------------------------------------+ |
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207 | | Function Prototypes. |
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208 | +--------------------------------------------------------------------------*/ |
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209 | /* |
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210 | * ------------------------ Intel 8259 (or emulation) Mngt Routines ------- |
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211 | */ |
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212 | |
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213 | /** |
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214 | * @name Function Prototypes |
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215 | * @{ |
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216 | */ |
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217 | |
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218 | void BSP_i8259s_init(void); |
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219 | |
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220 | /** |
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221 | * @brief function to disable a particular irq at 8259 level. |
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222 | * |
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223 | * After calling this function, even if the device asserts the interrupt |
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224 | * line it will not be propagated further to the processor. |
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225 | * |
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226 | * @retval 1 the interrupt was enabled originally |
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227 | * @retval 0 the interrupt was disabled originally |
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228 | * @retval <0 error |
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229 | */ |
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230 | int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine); |
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231 | |
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232 | /** |
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233 | * @brief function to enable a particular irq at 8259 level. |
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234 | * |
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235 | * After calling this function, if the device asserts the interrupt line |
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236 | * it will be propagated further to the processor. |
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237 | */ |
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238 | int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine); |
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239 | |
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240 | /** |
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241 | * @brief function to acknowledge a particular irq at 8259 level. |
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242 | * |
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243 | * After calling this function, if a device asserts an enabled interrupt |
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244 | * line it will be propagated further to the processor. Mainly useful for |
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245 | * people writing raw handlers as this is automagically done for RTEMS managed |
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246 | * handlers. |
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247 | */ |
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248 | int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine); |
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249 | |
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250 | /** |
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251 | * @brief function to check if a particular irq is enabled at 8259 level. |
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252 | */ |
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253 | int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine); |
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254 | |
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255 | int BSP_i8259s_int_process(void); |
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256 | |
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257 | extern void BSP_rtems_irq_mng_init(unsigned cpuId); |
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258 | extern void BSP_i8259s_init(void); |
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259 | |
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260 | /** @} */ |
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261 | |
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262 | /** @} */ |
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263 | |
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264 | #ifdef __cplusplus |
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265 | }; |
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266 | #endif |
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267 | |
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268 | #endif |
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269 | #endif |
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