[0b91d327] | 1 | /* exception.S |
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| 2 | * |
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| 3 | * This file contains a customized MIPS exception handler. |
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| 4 | * It hooks into the exception handler present in the resident |
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| 5 | * PMON debug monitor. |
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| 6 | * |
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| 7 | * Author: Bruce Robinson |
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| 8 | * |
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| 9 | * This code was derived from cpu_asm.S with the following copyright: |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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| 12 | * |
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| 13 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 14 | * without any express or implied warranty: |
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| 15 | * permission to use, copy, modify, and distribute this file |
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| 16 | * for any purpose is hereby granted without fee, provided that |
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| 17 | * the above copyright notice and this notice appears in all |
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| 18 | * copies, and that the name of Transition Networks not be used in |
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| 19 | * advertising or publicity pertaining to distribution of the |
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| 20 | * software without specific, written prior permission. |
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| 21 | * Transition Networks makes no representations about the suitability |
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| 22 | * of this software for any purpose. |
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| 23 | * |
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| 24 | * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s: |
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| 25 | * |
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[a68347d] | 26 | * COPYRIGHT (c) 1989-2010. |
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[0b91d327] | 27 | * On-Line Applications Research Corporation (OAR). |
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| 28 | * |
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| 29 | * The license and distribution terms for this file may be |
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| 30 | * found in the file LICENSE in this distribution or at |
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[c499856] | 31 | * http://www.rtems.org/license/LICENSE. |
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[0b91d327] | 32 | */ |
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| 33 | |
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[a68347d] | 34 | #include <bspopts.h> |
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| 35 | #include <rtems/asm.h> |
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[5a0b7914] | 36 | #include <rtems/score/percpu.h> |
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[0b91d327] | 37 | #include <rtems/mips/iregdef.h> |
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| 38 | #include <rtems/mips/idtcpu.h> |
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[a68347d] | 39 | #if BSP_HAS_USC320 |
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| 40 | #include <usc.h> |
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| 41 | #endif |
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[0b91d327] | 42 | |
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| 43 | #if __mips == 3 |
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| 44 | /* 64 bit register operations */ |
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| 45 | #define NOP nop |
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| 46 | #define ADD dadd |
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| 47 | #define STREG sd |
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| 48 | #define LDREG ld |
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| 49 | #define ADDU addu |
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| 50 | #define ADDIU addiu |
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| 51 | #define STREGC1 sdc1 |
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| 52 | #define LDREGC1 ldc1 |
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| 53 | #define R_SZ 8 |
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| 54 | #define F_SZ 8 |
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| 55 | #define SZ_INT 8 |
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| 56 | #define SZ_INT_POW2 3 |
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| 57 | |
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| 58 | /* XXX if we don't always want 64 bit register ops, then another ifdef */ |
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| 59 | |
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| 60 | #elif __mips == 1 |
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| 61 | /* 32 bit register operations*/ |
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| 62 | #define NOP nop |
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| 63 | #define ADD add |
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| 64 | #define STREG sw |
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| 65 | #define LDREG lw |
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| 66 | #define ADDU add |
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| 67 | #define ADDIU addi |
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| 68 | #define STREGC1 swc1 |
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| 69 | #define LDREGC1 lwc1 |
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| 70 | #define R_SZ 4 |
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| 71 | #define F_SZ 4 |
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| 72 | #define SZ_INT 4 |
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| 73 | #define SZ_INT_POW2 2 |
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| 74 | #else |
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| 75 | #error "mips assembly: what size registers do I deal with?" |
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| 76 | #endif |
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| 77 | |
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| 78 | |
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| 79 | #define ISR_VEC_SIZE 4 |
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| 80 | #define EXCP_STACK_SIZE (NREGS*R_SZ) |
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| 81 | |
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| 82 | |
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| 83 | #ifdef __GNUC__ |
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| 84 | #define EXTERN(x,size) .extern x,size |
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| 85 | #else |
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| 86 | #define EXTERN(x,size) |
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| 87 | #endif |
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| 88 | |
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| 89 | |
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| 90 | .extern _Thread_Dispatch |
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| 91 | |
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| 92 | /* void __ISR_Handler() |
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| 93 | * |
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| 94 | * This routine provides the RTEMS interrupt management. |
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| 95 | * |
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| 96 | */ |
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| 97 | |
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| 98 | #if 0 |
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| 99 | void _ISR_Handler() |
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| 100 | { |
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| 101 | /* |
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| 102 | * This discussion ignores a lot of the ugly details in a real |
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| 103 | * implementation such as saving enough registers/state to be |
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| 104 | * able to do something real. Keep in mind that the goal is |
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| 105 | * to invoke a user's ISR handler which is written in C and |
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| 106 | * uses a certain set of registers. |
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| 107 | * |
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| 108 | * Also note that the exact order is to a large extent flexible. |
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| 109 | * Hardware will dictate a sequence for a certain subset of |
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| 110 | * _ISR_Handler while requirements for setting |
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| 111 | */ |
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| 112 | |
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| 113 | /* |
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| 114 | * At entry to "common" _ISR_Handler, the vector number must be |
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| 115 | * available. On some CPUs the hardware puts either the vector |
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| 116 | * number or the offset into the vector table for this ISR in a |
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| 117 | * known place. If the hardware does not give us this information, |
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| 118 | * then the assembly portion of RTEMS for this port will contain |
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| 119 | * a set of distinct interrupt entry points which somehow place |
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| 120 | * the vector number in a known place (which is safe if another |
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| 121 | * interrupt nests this one) and branches to _ISR_Handler. |
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| 122 | * |
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| 123 | */ |
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| 124 | #endif |
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| 125 | FRAME(bsp_ISR_Handler,sp,0,ra) |
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| 126 | .set noreorder |
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| 127 | |
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| 128 | #if 0 |
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| 129 | /* Activate TX49xx PIO19 signal for diagnostics */ |
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| 130 | lui k0,0xff1f |
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| 131 | ori k0,k0,0xf500 |
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| 132 | lw k0,(k0) |
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| 133 | lui k1,0x8 |
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| 134 | or k1,k1,k0 |
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| 135 | lui k0,0xff1f |
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| 136 | ori k0,k0,0xf500 |
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| 137 | sw k1,(k0) |
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| 138 | #endif |
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| 139 | mfc0 k0,C0_CAUSE /* Determine if an interrupt generated this exception */ |
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| 140 | nop |
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| 141 | and k1,k0,CAUSE_EXCMASK |
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| 142 | beq k1,zero,_chk_int /* If so, branch to service here */ |
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| 143 | nop |
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| 144 | la k0,_int_esr_link /* Otherwise, jump to next exception handler in PMON exception chain */ |
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| 145 | lw k0,(k0) |
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| 146 | lw k0,4(k0) |
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| 147 | j k0 |
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| 148 | nop |
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| 149 | _chk_int: |
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| 150 | mfc0 k1,C0_SR |
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| 151 | nop |
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| 152 | and k0,k1 |
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[a68347d] | 153 | #if HAS_RM52xx |
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| 154 | and k0,CAUSE_IPMASK |
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| 155 | #elif HAS_TX49xx |
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[0b91d327] | 156 | and k0,(SR_IBIT1 | SR_IBIT2 | SR_IBIT3) |
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[a68347d] | 157 | #endif |
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| 158 | /* external interrupt not enabled, ignore */ |
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| 159 | beq k0,zero,_ISR_Handler_quick_exit |
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[0b91d327] | 160 | nop |
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| 161 | |
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| 162 | /* For debugging interrupts, clear EXL to allow breakpoints */ |
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| 163 | #if 0 |
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| 164 | MFC0 k0, C0_SR |
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| 165 | #if __mips == 3 |
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| 166 | li k1,SR_EXL /* Clear EXL and Set IE to enable interrupts */ |
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| 167 | not k1 |
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| 168 | and k0,k1 |
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| 169 | li k1,SR_IE |
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| 170 | #elif __mips == 1 |
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| 171 | li k1,SR_IEC |
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| 172 | #endif |
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| 173 | or k0, k1 |
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| 174 | mtc0 k0, C0_SR |
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| 175 | NOP |
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| 176 | #endif |
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| 177 | |
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| 178 | |
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| 179 | /* |
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| 180 | * save some or all context on stack |
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| 181 | * may need to save some special interrupt information for exit |
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| 182 | */ |
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| 183 | |
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| 184 | /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */ |
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| 185 | |
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| 186 | /* wastes a lot of stack space for context?? */ |
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| 187 | ADDIU sp,sp,-EXCP_STACK_SIZE |
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| 188 | |
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| 189 | STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */ |
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| 190 | STREG v0, R_V0*R_SZ(sp) |
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| 191 | STREG v1, R_V1*R_SZ(sp) |
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| 192 | STREG a0, R_A0*R_SZ(sp) |
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| 193 | STREG a1, R_A1*R_SZ(sp) |
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| 194 | STREG a2, R_A2*R_SZ(sp) |
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| 195 | STREG a3, R_A3*R_SZ(sp) |
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| 196 | STREG t0, R_T0*R_SZ(sp) |
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| 197 | STREG t1, R_T1*R_SZ(sp) |
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| 198 | STREG t2, R_T2*R_SZ(sp) |
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| 199 | STREG t3, R_T3*R_SZ(sp) |
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| 200 | STREG t4, R_T4*R_SZ(sp) |
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| 201 | STREG t5, R_T5*R_SZ(sp) |
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| 202 | STREG t6, R_T6*R_SZ(sp) |
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| 203 | STREG t7, R_T7*R_SZ(sp) |
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| 204 | mflo t0 |
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| 205 | STREG t8, R_T8*R_SZ(sp) |
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| 206 | STREG t0, R_MDLO*R_SZ(sp) |
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| 207 | STREG t9, R_T9*R_SZ(sp) |
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| 208 | mfhi t0 |
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| 209 | STREG gp, R_GP*R_SZ(sp) |
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| 210 | STREG t0, R_MDHI*R_SZ(sp) |
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| 211 | STREG fp, R_FP*R_SZ(sp) |
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| 212 | |
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| 213 | .set noat |
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| 214 | STREG AT, R_AT*R_SZ(sp) |
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| 215 | .set at |
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| 216 | |
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| 217 | mfc0 t0,C0_SR |
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| 218 | dmfc0 t1,C0_EPC |
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| 219 | STREG t0,R_SR*R_SZ(sp) |
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| 220 | STREG t1,R_EPC*R_SZ(sp) |
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| 221 | |
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| 222 | /* |
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| 223 | * |
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| 224 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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| 225 | * if ( _ISR_Nest_level == 0 ) |
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| 226 | * switch to software interrupt stack |
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| 227 | * #endif |
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| 228 | */ |
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| 229 | |
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| 230 | /* |
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| 231 | * _ISR_Nest_level++; |
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| 232 | */ |
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[5a0b7914] | 233 | lw t0,ISR_NEST_LEVEL |
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[0b91d327] | 234 | NOP |
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| 235 | add t0,t0,1 |
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[5a0b7914] | 236 | sw t0,ISR_NEST_LEVEL |
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[0b91d327] | 237 | /* |
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| 238 | * _Thread_Dispatch_disable_level++; |
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| 239 | */ |
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[d19cce29] | 240 | lw t1,THREAD_DISPATCH_DISABLE_LEVEL |
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[0b91d327] | 241 | NOP |
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| 242 | add t1,t1,1 |
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[d19cce29] | 243 | sw t1,THREAD_DISPATCH_DISABLE_LEVEL |
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[0b91d327] | 244 | |
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[a68347d] | 245 | /* DEBUG - Add the following code to disable interrupts and clear |
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| 246 | * EXL in status register, this will allow memory |
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| 247 | * exceptions to occur while servicing the current interrupt |
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| 248 | */ |
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[0b91d327] | 249 | #if 0 |
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[a68347d] | 250 | /* Disable interrupts from internal interrupt controller */ |
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| 251 | li t0,~CAUSE_IP2_MASK |
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[0b91d327] | 252 | mfc0 t1,C0_SR |
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| 253 | nop |
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| 254 | and t1,t0 |
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| 255 | mtc0 t1,C0_SR |
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| 256 | nop |
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[a68347d] | 257 | /* Clear EXL in status register to allow memory exceptions to occur */ |
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| 258 | li t0,~SR_EXL |
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[0b91d327] | 259 | mfc0 t1,C0_SR |
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| 260 | nop |
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| 261 | and t1,t0 |
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| 262 | mtc0 t1,C0_SR |
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| 263 | nop |
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| 264 | #endif |
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| 265 | |
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| 266 | /* |
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| 267 | * Call the CPU model or BSP specific routine to decode the |
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| 268 | * interrupt source and actually vector to device ISR handlers. |
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| 269 | */ |
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| 270 | move a0,sp |
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| 271 | jal mips_vector_isr_handlers |
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| 272 | NOP |
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| 273 | |
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| 274 | /* Add the following code to disable interrupts (see DEBUG above) */ |
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| 275 | #if 0 |
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| 276 | li t0,SR_EXL /* Set EXL to hold off interrupts */ |
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| 277 | mfc0 t1,C0_SR |
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| 278 | nop |
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| 279 | or t1,t0 |
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| 280 | mtc0 t1,C0_SR |
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| 281 | nop |
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[a68347d] | 282 | /* Enable interrupts from internal interrupt controller */ |
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| 283 | li t0,CAUSE_IP2_MASK |
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[0b91d327] | 284 | mfc0 t1,C0_SR |
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| 285 | nop |
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| 286 | or t1,t0 |
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| 287 | mtc0 t1,C0_SR |
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| 288 | nop |
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| 289 | #endif |
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| 290 | |
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| 291 | _ISR_Handler_cleanup: |
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| 292 | |
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| 293 | /* |
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| 294 | * --_ISR_Nest_level; |
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| 295 | */ |
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[5a0b7914] | 296 | lw t2,ISR_NEST_LEVEL |
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[0b91d327] | 297 | NOP |
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| 298 | add t2,t2,-1 |
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[5a0b7914] | 299 | sw t2,ISR_NEST_LEVEL |
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[0b91d327] | 300 | /* |
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| 301 | * --_Thread_Dispatch_disable_level; |
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| 302 | */ |
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[d19cce29] | 303 | lw t1,THREAD_DISPATCH_DISABLE_LEVEL |
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[0b91d327] | 304 | NOP |
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| 305 | add t1,t1,-1 |
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[d19cce29] | 306 | sw t1,THREAD_DISPATCH_DISABLE_LEVEL |
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[0b91d327] | 307 | /* |
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| 308 | * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) |
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| 309 | * goto the label "exit interrupt (simple case)" |
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| 310 | */ |
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| 311 | or t0,t2,t1 |
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| 312 | bne t0,zero,_ISR_Handler_exit |
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| 313 | NOP |
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| 314 | |
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| 315 | |
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| 316 | /* |
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| 317 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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| 318 | * restore stack |
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| 319 | * #endif |
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| 320 | * |
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[1973a2a6] | 321 | * if ( !_Thread_Dispatch_necessary ) |
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[0b91d327] | 322 | * goto the label "exit interrupt (simple case)" |
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| 323 | */ |
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[5a0b7914] | 324 | lb t0,DISPATCH_NEEDED |
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[0b91d327] | 325 | NOP |
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[5a0b7914] | 326 | or t0,t0,t0 |
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[0b91d327] | 327 | beq t0,zero,_ISR_Handler_exit |
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| 328 | NOP |
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| 329 | |
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| 330 | /* |
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| 331 | ** Turn on interrupts before entering Thread_Dispatch which |
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| 332 | ** will run for a while, thus allowing new interrupts to |
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| 333 | ** be serviced. Observe the Thread_Dispatch_disable_level interlock |
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| 334 | ** that prevents recursive entry into Thread_Dispatch. |
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| 335 | */ |
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| 336 | |
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| 337 | mfc0 t0, C0_SR |
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| 338 | #if __mips == 3 |
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| 339 | li t1,SR_EXL /* Clear EXL and Set IE to enable interrupts */ |
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| 340 | not t1 |
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| 341 | and t0,t1 |
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| 342 | li t1,SR_IE |
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| 343 | #elif __mips == 1 |
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| 344 | li t1,SR_IEC |
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| 345 | #endif |
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| 346 | or t0, t1 |
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| 347 | mtc0 t0, C0_SR |
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| 348 | NOP |
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| 349 | |
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| 350 | /* save off our stack frame so the context switcher can get to it */ |
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| 351 | la t0,__exceptionStackFrame |
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| 352 | STREG sp,(t0) |
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| 353 | |
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| 354 | jal _Thread_Dispatch |
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| 355 | NOP |
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| 356 | |
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| 357 | /* and make sure its clear in case we didn't dispatch. if we did, its |
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| 358 | ** already cleared */ |
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| 359 | la t0,__exceptionStackFrame |
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| 360 | STREG zero,(t0) |
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| 361 | NOP |
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| 362 | |
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| 363 | /* |
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| 364 | ** turn interrupts back off while we restore context so |
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| 365 | ** a badly timed interrupt won't accidentally mess things up |
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| 366 | */ |
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| 367 | mfc0 t0, C0_SR |
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| 368 | #if __mips == 3 |
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| 369 | li t1,SR_IE /* Clear IE first (recommended) */ |
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| 370 | not t1 |
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| 371 | and t0,t1 |
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| 372 | mtc0 t0, C0_SR |
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| 373 | li t1,SR_EXL | SR_IE /* Set EXL and IE, this puts status register bits back to interrupted state */ |
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| 374 | or t0,t1 |
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| 375 | #elif __mips == 1 |
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| 376 | /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */ |
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| 377 | li t1,SR_IEC | SR_KUP | SR_KUC |
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| 378 | not t1 |
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| 379 | and t0, t1 |
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| 380 | #endif |
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| 381 | mtc0 t0, C0_SR |
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| 382 | NOP |
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| 383 | |
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| 384 | /* |
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| 385 | * prepare to get out of interrupt |
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| 386 | * return from interrupt (maybe to _ISR_Dispatch) |
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| 387 | * |
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| 388 | * LABEL "exit interrupt (simple case):" |
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| 389 | * prepare to get out of interrupt |
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| 390 | * return from interrupt |
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| 391 | */ |
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| 392 | |
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| 393 | _ISR_Handler_exit: |
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| 394 | |
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| 395 | /* restore interrupt context from stack */ |
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| 396 | LDREG t8, R_MDLO*R_SZ(sp) |
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| 397 | LDREG t0, R_T0*R_SZ(sp) |
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| 398 | mtlo t8 |
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| 399 | LDREG t8, R_MDHI*R_SZ(sp) |
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| 400 | LDREG t1, R_T1*R_SZ(sp) |
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| 401 | mthi t8 |
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| 402 | LDREG t2, R_T2*R_SZ(sp) |
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| 403 | LDREG t3, R_T3*R_SZ(sp) |
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| 404 | LDREG t4, R_T4*R_SZ(sp) |
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| 405 | LDREG t5, R_T5*R_SZ(sp) |
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| 406 | LDREG t6, R_T6*R_SZ(sp) |
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| 407 | LDREG t7, R_T7*R_SZ(sp) |
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| 408 | LDREG t8, R_T8*R_SZ(sp) |
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| 409 | LDREG t9, R_T9*R_SZ(sp) |
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| 410 | LDREG gp, R_GP*R_SZ(sp) |
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| 411 | LDREG fp, R_FP*R_SZ(sp) |
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| 412 | LDREG ra, R_RA*R_SZ(sp) |
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| 413 | LDREG a0, R_A0*R_SZ(sp) |
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| 414 | LDREG a1, R_A1*R_SZ(sp) |
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| 415 | LDREG a2, R_A2*R_SZ(sp) |
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| 416 | LDREG a3, R_A3*R_SZ(sp) |
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| 417 | LDREG v1, R_V1*R_SZ(sp) |
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| 418 | LDREG v0, R_V0*R_SZ(sp) |
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| 419 | |
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| 420 | LDREG k1, R_EPC*R_SZ(sp) |
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| 421 | mtc0 k1,C0_EPC |
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| 422 | |
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| 423 | .set noat |
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| 424 | LDREG AT, R_AT*R_SZ(sp) |
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| 425 | .set at |
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| 426 | |
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| 427 | ADDIU sp,sp,EXCP_STACK_SIZE |
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| 428 | |
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| 429 | _ISR_Handler_quick_exit: |
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| 430 | eret |
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| 431 | nop |
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| 432 | |
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| 433 | |
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[a68347d] | 434 | #if BSP_HAS_USC320 |
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| 435 | /* Interrupts from USC320 are serviced here */ |
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| 436 | .global USC_isr |
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| 437 | .extern Clock_isr |
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| 438 | USC_isr: |
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| 439 | /* check if it's a USC320 heartbeat interrupt */ |
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| 440 | la k0,INT_STAT /* read INT_STAT register */ |
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| 441 | lw k0,(k0) |
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| 442 | nop /* reading from external device */ |
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| 443 | sll k0,(31-21) /* test bit 21 (HBI) */ |
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| 444 | |
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| 445 | bgez k0,USC_isr2 /* branch if not a heartbeat interrupt */ |
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| 446 | NOP |
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| 447 | |
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| 448 | /* clear the heartbeat interrupt */ |
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| 449 | la k0,INT_STAT |
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| 450 | li t0,HBI_MASK |
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| 451 | sw t0,(k0) |
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| 452 | /* wait for interrupt to clear */ |
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| 453 | USC_isr1: |
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| 454 | la k0,INT_STAT /* read INT_STAT register */ |
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| 455 | lw k0,(k0) |
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| 456 | nop /* reading from external device */ |
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| 457 | sll k0,(31-21) /* test bit 21 (HBI) */ |
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| 458 | bltz k0,USC_isr1 /* branch if bit set */ |
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| 459 | nop |
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| 460 | j Clock_isr /* Jump to clock isr */ |
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| 461 | nop |
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| 462 | USC_isr2: |
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| 463 | j ra /* no serviceable interrupt, return without doing anything */ |
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| 464 | nop |
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| 465 | #endif |
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| 466 | |
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[0b91d327] | 467 | #if 0 |
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| 468 | .global int7_isr |
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| 469 | .extern Interrupt_7_isr |
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| 470 | int7_isr: |
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| 471 | /* Verify interrupt is from Timer */ |
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| 472 | la k0,IRCS /* read Interrupt Current Status register */ |
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| 473 | lw k0,(k0) |
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| 474 | nop /* reading from external device */ |
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| 475 | li k1,IRCS_CAUSE_MASK |
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| 476 | and k0,k0,k1 /* isolate interrupt cause */ |
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| 477 | |
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| 478 | li k1,INT7INT /* test for interrupt 7 */ |
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| 479 | subu k1,k0,k1 |
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| 480 | beq k1,zero,int7_isr1 |
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| 481 | nop |
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| 482 | j ra /* interrupt 7 no longer valid, return without doing anything */ |
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| 483 | nop |
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| 484 | int7_isr1: |
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| 485 | j Interrupt_7_isr /* Jump to Interrupt 7 isr */ |
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| 486 | nop |
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| 487 | #endif |
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| 488 | |
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| 489 | .set reorder |
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| 490 | |
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| 491 | ENDFRAME(bsp_ISR_Handler) |
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| 492 | |
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| 493 | |
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| 494 | FRAME(_BRK_Handler,sp,0,ra) |
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| 495 | .set noreorder |
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| 496 | |
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[a68347d] | 497 | #if BSP_HAS_USC320 |
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[0b91d327] | 498 | la k0,INT_CFG3 /* Disable heartbeat interrupt in USC320, it interferes with PMON exception handler */ |
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| 499 | lw k1,(k0) |
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| 500 | li k0,~HBI_MASK |
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| 501 | and k1,k1,k0 |
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| 502 | la k0,INT_CFG3 |
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| 503 | sw k1,(k0) |
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| 504 | #endif |
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| 505 | |
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| 506 | la k0,_brk_esr_link /* Jump to next exception handler in PMON exception chain */ |
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| 507 | lw k0,(k0) |
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| 508 | lw k0,4(k0) |
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| 509 | j k0 |
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| 510 | nop |
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| 511 | |
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| 512 | .set reorder |
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| 513 | ENDFRAME(_BRK_Handler) |
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| 514 | |
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| 515 | |
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| 516 | /************************************************************************** |
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| 517 | ** |
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| 518 | ** init_exc_vecs() - moves the exception code into the addresses |
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| 519 | ** reserved for exception vectors |
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| 520 | ** |
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| 521 | ** UTLB Miss exception vector at address 0x80000000 |
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| 522 | ** |
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| 523 | ** General exception vector at address 0x80000080 |
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| 524 | ** |
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| 525 | ** RESET exception vector is at address 0xbfc00000 |
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| 526 | ** |
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| 527 | ***************************************************************************/ |
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| 528 | |
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| 529 | FRAME(init_exc_vecs,sp,0,ra) |
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| 530 | .set noreorder |
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| 531 | |
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| 532 | .extern mon_onintr |
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| 533 | |
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| 534 | /* Install interrupt handler in PMON exception handling chain */ |
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| 535 | |
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| 536 | addiu sp,sp,-8 |
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| 537 | sw ra,(sp) /* Save ra contents on stack */ |
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| 538 | move a0,zero |
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| 539 | la a1,_int_esr_link |
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| 540 | jal mon_onintr /* Make PMON system call to install interrupt exception handler */ |
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| 541 | nop |
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| 542 | li a0,9 |
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| 543 | la a1,_brk_esr_link |
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| 544 | jal mon_onintr /* Make PMON system call to install break exception handler */ |
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| 545 | nop |
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| 546 | lw ra,(sp) |
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| 547 | addiu sp,sp,8 /* Restore ra contents from stack */ |
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| 548 | j ra |
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| 549 | nop |
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| 550 | |
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| 551 | .set reorder |
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| 552 | ENDFRAME(init_exc_vecs) |
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| 553 | |
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| 554 | |
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| 555 | #if 0 /* Unused code below */ |
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| 556 | |
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| 557 | /************************************************************* |
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| 558 | * enable_int7(ints) |
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| 559 | * Enable interrupt 7 |
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| 560 | */ |
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| 561 | FRAME(enable_int7,sp,0,ra) |
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| 562 | .set noreorder |
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| 563 | |
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| 564 | la t0,IRDM1 # Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low) |
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| 565 | li t1,0x0 |
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| 566 | sw t1,(t0) |
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| 567 | |
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| 568 | la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2) |
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| 569 | li t1,0x200 |
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| 570 | sw t1,(t0) |
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| 571 | |
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| 572 | la t0,IRMSK # Set interrupt controller mask |
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| 573 | li t1,0x0 |
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| 574 | sw t1,(t0) |
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| 575 | |
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| 576 | la t0,IRDEN # Enable interrupts from controller |
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| 577 | li t1,0x1 |
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| 578 | sw t1,(t0) |
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| 579 | |
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| 580 | j ra |
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| 581 | nop |
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| 582 | .set reorder |
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| 583 | ENDFRAME(enable_int7) |
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| 584 | |
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| 585 | /************************************************************* |
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| 586 | * disable_int7(ints) |
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| 587 | * Disable interrupt 7 |
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| 588 | */ |
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| 589 | FRAME(disable_int7,sp,0,ra) |
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| 590 | .set noreorder |
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| 591 | |
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| 592 | la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 0 to diasble int 7) |
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| 593 | li t1,0x200 |
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| 594 | sw t1,(t0) |
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| 595 | |
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| 596 | j ra |
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| 597 | nop |
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| 598 | .set reorder |
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| 599 | ENDFRAME(disable_int7) |
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| 600 | #endif |
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| 601 | |
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| 602 | /************************************************************* |
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| 603 | * exception: |
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| 604 | * Diagnostic code that can be hooked to PMON interrupt handler. |
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| 605 | * Generates pulse on PIO22 pin. |
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| 606 | * Called from _exception code in PMON (see mips.s of PMON). |
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| 607 | * Return address is located in k1. |
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| 608 | */ |
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| 609 | FRAME(tx49xxexception,sp,0,ra) |
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| 610 | .set noreorder |
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| 611 | la k0,k1tmp |
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| 612 | sw k1,(k0) |
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| 613 | |
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| 614 | /* Activate TX49xx PIO22 signal for diagnostics */ |
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| 615 | lui k0,0xff1f |
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| 616 | ori k0,k0,0xf500 |
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| 617 | lw k0,(k0) |
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| 618 | lui k1,0x40 |
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| 619 | or k1,k1,k0 |
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| 620 | lui k0,0xff1f |
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| 621 | ori k0,k0,0xf500 |
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| 622 | sw k1,(k0) |
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| 623 | nop |
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| 624 | |
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| 625 | /* De-activate TX49xx PIO22 signal for diagnostics */ |
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| 626 | lui k0,0xff1f |
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| 627 | ori k0,k0,0xf500 |
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| 628 | lw k0,(k0) |
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| 629 | lui k1,0x40 |
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| 630 | not k1 |
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| 631 | and k1,k1,k0 |
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| 632 | lui k0,0xff1f |
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| 633 | ori k0,k0,0xf500 |
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| 634 | sw k1,(k0) |
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| 635 | nop |
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| 636 | |
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| 637 | la k0,k1tmp |
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| 638 | lw k1,(k0) |
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| 639 | j k1 |
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| 640 | .set reorder |
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| 641 | ENDFRAME(tx49xxexception) |
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| 642 | |
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| 643 | |
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| 644 | |
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| 645 | |
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| 646 | .data |
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| 647 | |
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| 648 | k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */ |
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| 649 | |
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| 650 | /************************************************************* |
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| 651 | * |
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| 652 | * Exception handler links, used in PMON exception handler chains |
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| 653 | */ |
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| 654 | /* Interrupt exception service routine link */ |
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| 655 | .global _int_esr_link |
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| 656 | _int_esr_link: |
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| 657 | .word 0 |
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| 658 | .word bsp_ISR_Handler |
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| 659 | |
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| 660 | /* Break exception service routine link */ |
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| 661 | .global _brk_esr_link |
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| 662 | _brk_esr_link: |
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| 663 | .word 0 |
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| 664 | .word _BRK_Handler |
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| 665 | |
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| 666 | |
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| 667 | |
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| 668 | |
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