1 | /* exception.S |
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2 | * |
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3 | * This file contains a customized MIPS exception handler. |
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4 | * It hooks into the exception handler present in the resident |
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5 | * PMON debug monitor. |
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6 | * |
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7 | * Author: Bruce Robinson |
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8 | * |
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9 | * This code was derived from cpu_asm.S with the following copyright: |
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10 | * |
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11 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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12 | * |
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13 | * To anyone who acknowledges that this file is provided "AS IS" |
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14 | * without any express or implied warranty: |
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15 | * permission to use, copy, modify, and distribute this file |
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16 | * for any purpose is hereby granted without fee, provided that |
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17 | * the above copyright notice and this notice appears in all |
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18 | * copies, and that the name of Transition Networks not be used in |
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19 | * advertising or publicity pertaining to distribution of the |
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20 | * software without specific, written prior permission. |
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21 | * Transition Networks makes no representations about the suitability |
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22 | * of this software for any purpose. |
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23 | * |
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24 | * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s: |
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25 | * |
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26 | * COPYRIGHT (c) 1989-1999. |
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27 | * On-Line Applications Research Corporation (OAR). |
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28 | * |
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29 | * The license and distribution terms for this file may be |
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30 | * found in the file LICENSE in this distribution or at |
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31 | * http://www.OARcorp.com/rtems/license.html. |
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32 | * |
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33 | * $Id$ |
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34 | */ |
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35 | /* @(#)exception.S 7/27/04 1.00 */ |
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36 | |
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37 | #include <rtems/mips/iregdef.h> |
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38 | #include <rtems/mips/idtcpu.h> |
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39 | |
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40 | |
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41 | #define FRAME(name,frm_reg,offset,ret_reg) \ |
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42 | .globl name; \ |
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43 | .ent name; \ |
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44 | name:; \ |
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45 | .frame frm_reg,offset,ret_reg |
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46 | #define ENDFRAME(name) \ |
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47 | .end name |
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48 | |
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49 | |
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50 | #if __mips == 3 |
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51 | /* 64 bit register operations */ |
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52 | #define NOP nop |
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53 | #define ADD dadd |
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54 | #define STREG sd |
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55 | #define LDREG ld |
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56 | #define ADDU addu |
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57 | #define ADDIU addiu |
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58 | #define STREGC1 sdc1 |
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59 | #define LDREGC1 ldc1 |
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60 | #define R_SZ 8 |
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61 | #define F_SZ 8 |
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62 | #define SZ_INT 8 |
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63 | #define SZ_INT_POW2 3 |
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64 | |
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65 | /* XXX if we don't always want 64 bit register ops, then another ifdef */ |
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66 | |
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67 | #elif __mips == 1 |
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68 | /* 32 bit register operations*/ |
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69 | #define NOP nop |
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70 | #define ADD add |
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71 | #define STREG sw |
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72 | #define LDREG lw |
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73 | #define ADDU add |
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74 | #define ADDIU addi |
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75 | #define STREGC1 swc1 |
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76 | #define LDREGC1 lwc1 |
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77 | #define R_SZ 4 |
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78 | #define F_SZ 4 |
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79 | #define SZ_INT 4 |
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80 | #define SZ_INT_POW2 2 |
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81 | #else |
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82 | #error "mips assembly: what size registers do I deal with?" |
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83 | #endif |
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84 | |
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85 | |
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86 | #define ISR_VEC_SIZE 4 |
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87 | #define EXCP_STACK_SIZE (NREGS*R_SZ) |
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88 | |
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89 | |
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90 | #ifdef __GNUC__ |
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91 | #define EXTERN(x,size) .extern x,size |
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92 | #else |
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93 | #define EXTERN(x,size) |
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94 | #endif |
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95 | |
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96 | |
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97 | EXTERN(_ISR_Nest_level, 4) |
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98 | EXTERN(_Thread_Dispatch_disable_level,4) |
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99 | EXTERN(_Context_Switch_necessary,4) |
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100 | EXTERN(_ISR_Signals_to_thread_executing,4) |
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101 | .extern _Thread_Dispatch |
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102 | .extern _ISR_Vector_table |
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103 | |
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104 | /* void __ISR_Handler() |
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105 | * |
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106 | * This routine provides the RTEMS interrupt management. |
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107 | * |
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108 | */ |
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109 | |
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110 | #if 0 |
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111 | void _ISR_Handler() |
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112 | { |
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113 | /* |
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114 | * This discussion ignores a lot of the ugly details in a real |
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115 | * implementation such as saving enough registers/state to be |
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116 | * able to do something real. Keep in mind that the goal is |
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117 | * to invoke a user's ISR handler which is written in C and |
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118 | * uses a certain set of registers. |
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119 | * |
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120 | * Also note that the exact order is to a large extent flexible. |
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121 | * Hardware will dictate a sequence for a certain subset of |
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122 | * _ISR_Handler while requirements for setting |
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123 | */ |
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124 | |
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125 | /* |
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126 | * At entry to "common" _ISR_Handler, the vector number must be |
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127 | * available. On some CPUs the hardware puts either the vector |
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128 | * number or the offset into the vector table for this ISR in a |
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129 | * known place. If the hardware does not give us this information, |
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130 | * then the assembly portion of RTEMS for this port will contain |
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131 | * a set of distinct interrupt entry points which somehow place |
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132 | * the vector number in a known place (which is safe if another |
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133 | * interrupt nests this one) and branches to _ISR_Handler. |
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134 | * |
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135 | */ |
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136 | #endif |
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137 | FRAME(rbtx4938_ISR_Handler,sp,0,ra) |
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138 | .set noreorder |
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139 | |
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140 | #if 0 |
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141 | /* Activate TX4938 PIO19 signal for diagnostics */ |
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142 | lui k0,0xff1f |
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143 | ori k0,k0,0xf500 |
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144 | lw k0,(k0) |
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145 | lui k1,0x8 |
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146 | or k1,k1,k0 |
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147 | lui k0,0xff1f |
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148 | ori k0,k0,0xf500 |
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149 | sw k1,(k0) |
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150 | #endif |
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151 | |
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152 | mfc0 k0,C0_CAUSE /* Determine if an interrupt generated this exception */ |
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153 | nop |
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154 | and k1,k0,CAUSE_EXCMASK |
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155 | beq k1,zero,_chk_int /* If so, branch to service here */ |
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156 | nop |
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157 | la k0,_int_esr_link /* Otherwise, jump to next exception handler in PMON exception chain */ |
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158 | lw k0,(k0) |
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159 | lw k0,4(k0) |
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160 | j k0 |
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161 | nop |
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162 | _chk_int: |
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163 | mfc0 k1,C0_SR |
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164 | nop |
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165 | and k0,k1 |
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166 | and k0,(SR_IBIT1 | SR_IBIT2 | SR_IBIT3) |
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167 | beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */ |
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168 | nop |
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169 | |
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170 | /* For debugging interrupts, clear EXL to allow breakpoints */ |
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171 | #if 0 |
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172 | MFC0 k0, C0_SR |
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173 | li k1,SR_EXL /* Clear EXL and Set IE to enable interrupts */ |
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174 | not k1 |
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175 | and k0,k1 |
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176 | li k1,SR_IE |
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177 | or k0, k1 |
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178 | mtc0 k0, C0_SR |
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179 | NOP |
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180 | #endif |
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181 | |
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182 | |
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183 | /* |
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184 | * save some or all context on stack |
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185 | * may need to save some special interrupt information for exit |
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186 | */ |
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187 | |
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188 | /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */ |
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189 | |
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190 | /* wastes a lot of stack space for context?? */ |
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191 | ADDIU sp,sp,-EXCP_STACK_SIZE |
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192 | |
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193 | STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */ |
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194 | STREG v0, R_V0*R_SZ(sp) |
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195 | STREG v1, R_V1*R_SZ(sp) |
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196 | STREG a0, R_A0*R_SZ(sp) |
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197 | STREG a1, R_A1*R_SZ(sp) |
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198 | STREG a2, R_A2*R_SZ(sp) |
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199 | STREG a3, R_A3*R_SZ(sp) |
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200 | STREG t0, R_T0*R_SZ(sp) |
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201 | STREG t1, R_T1*R_SZ(sp) |
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202 | STREG t2, R_T2*R_SZ(sp) |
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203 | STREG t3, R_T3*R_SZ(sp) |
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204 | STREG t4, R_T4*R_SZ(sp) |
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205 | STREG t5, R_T5*R_SZ(sp) |
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206 | STREG t6, R_T6*R_SZ(sp) |
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207 | STREG t7, R_T7*R_SZ(sp) |
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208 | mflo t0 |
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209 | STREG t8, R_T8*R_SZ(sp) |
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210 | STREG t0, R_MDLO*R_SZ(sp) |
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211 | STREG t9, R_T9*R_SZ(sp) |
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212 | mfhi t0 |
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213 | STREG gp, R_GP*R_SZ(sp) |
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214 | STREG t0, R_MDHI*R_SZ(sp) |
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215 | STREG fp, R_FP*R_SZ(sp) |
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216 | |
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217 | .set noat |
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218 | STREG AT, R_AT*R_SZ(sp) |
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219 | .set at |
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220 | |
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221 | mfc0 t0,C0_SR |
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222 | dmfc0 t1,C0_EPC |
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223 | STREG t0,R_SR*R_SZ(sp) |
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224 | STREG t1,R_EPC*R_SZ(sp) |
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225 | |
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226 | /* |
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227 | * |
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228 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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229 | * if ( _ISR_Nest_level == 0 ) |
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230 | * switch to software interrupt stack |
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231 | * #endif |
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232 | */ |
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233 | |
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234 | /* |
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235 | * _ISR_Nest_level++; |
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236 | */ |
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237 | lw t0,_ISR_Nest_level |
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238 | NOP |
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239 | add t0,t0,1 |
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240 | sw t0,_ISR_Nest_level |
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241 | /* |
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242 | * _Thread_Dispatch_disable_level++; |
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243 | */ |
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244 | lw t1,_Thread_Dispatch_disable_level |
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245 | NOP |
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246 | add t1,t1,1 |
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247 | sw t1,_Thread_Dispatch_disable_level |
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248 | |
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249 | |
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250 | /* DEBUG - Add the following code to disable interrupts and clear EXL in status register, this will |
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251 | allow memory exceptions to occur while servicing the current interrupt */ |
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252 | #if 0 |
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253 | li t0,~CAUSE_IP2_MASK /* Disable interrupts from internal interrupt controller */ |
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254 | mfc0 t1,C0_SR |
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255 | nop |
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256 | and t1,t0 |
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257 | mtc0 t1,C0_SR |
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258 | nop |
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259 | li t0,~SR_EXL /* Clear EXL in status register to allow memory exceptions to occur */ |
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260 | mfc0 t1,C0_SR |
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261 | nop |
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262 | and t1,t0 |
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263 | mtc0 t1,C0_SR |
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264 | nop |
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265 | #endif |
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266 | |
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267 | /* |
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268 | * Call the CPU model or BSP specific routine to decode the |
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269 | * interrupt source and actually vector to device ISR handlers. |
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270 | */ |
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271 | move a0,sp |
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272 | jal mips_vector_isr_handlers |
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273 | NOP |
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274 | |
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275 | /* Add the following code to disable interrupts (see DEBUG above) */ |
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276 | #if 0 |
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277 | li t0,SR_EXL /* Set EXL to hold off interrupts */ |
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278 | mfc0 t1,C0_SR |
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279 | nop |
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280 | or t1,t0 |
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281 | mtc0 t1,C0_SR |
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282 | nop |
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283 | li t0,CAUSE_IP2_MASK /* Enable interrupts from internal interrupt controller */ |
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284 | mfc0 t1,C0_SR |
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285 | nop |
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286 | or t1,t0 |
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287 | mtc0 t1,C0_SR |
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288 | nop |
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289 | #endif |
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290 | |
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291 | _ISR_Handler_cleanup: |
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292 | |
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293 | /* |
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294 | * --_ISR_Nest_level; |
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295 | */ |
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296 | lw t2,_ISR_Nest_level |
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297 | NOP |
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298 | add t2,t2,-1 |
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299 | sw t2,_ISR_Nest_level |
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300 | /* |
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301 | * --_Thread_Dispatch_disable_level; |
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302 | */ |
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303 | lw t1,_Thread_Dispatch_disable_level |
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304 | NOP |
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305 | add t1,t1,-1 |
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306 | sw t1,_Thread_Dispatch_disable_level |
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307 | /* |
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308 | * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) |
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309 | * goto the label "exit interrupt (simple case)" |
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310 | */ |
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311 | or t0,t2,t1 |
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312 | bne t0,zero,_ISR_Handler_exit |
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313 | NOP |
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314 | |
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315 | |
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316 | /* |
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317 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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318 | * restore stack |
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319 | * #endif |
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320 | * |
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321 | * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) |
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322 | * goto the label "exit interrupt (simple case)" |
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323 | */ |
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324 | lw t0,_Context_Switch_necessary |
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325 | lw t1,_ISR_Signals_to_thread_executing |
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326 | NOP |
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327 | or t0,t0,t1 |
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328 | beq t0,zero,_ISR_Handler_exit |
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329 | NOP |
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330 | |
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331 | /* |
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332 | ** Turn on interrupts before entering Thread_Dispatch which |
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333 | ** will run for a while, thus allowing new interrupts to |
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334 | ** be serviced. Observe the Thread_Dispatch_disable_level interlock |
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335 | ** that prevents recursive entry into Thread_Dispatch. |
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336 | */ |
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337 | |
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338 | mfc0 t0, C0_SR |
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339 | #if __mips == 3 |
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340 | li t1,SR_EXL /* Clear EXL and Set IE to enable interrupts */ |
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341 | not t1 |
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342 | and t0,t1 |
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343 | li t1,SR_IE |
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344 | #elif __mips == 1 |
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345 | li t1,SR_IEC |
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346 | #endif |
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347 | or t0, t1 |
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348 | mtc0 t0, C0_SR |
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349 | NOP |
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350 | |
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351 | /* save off our stack frame so the context switcher can get to it */ |
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352 | la t0,__exceptionStackFrame |
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353 | STREG sp,(t0) |
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354 | |
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355 | jal _Thread_Dispatch |
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356 | NOP |
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357 | |
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358 | /* and make sure its clear in case we didn't dispatch. if we did, its |
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359 | ** already cleared */ |
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360 | la t0,__exceptionStackFrame |
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361 | STREG zero,(t0) |
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362 | NOP |
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363 | |
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364 | /* |
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365 | ** turn interrupts back off while we restore context so |
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366 | ** a badly timed interrupt won't accidentally mess things up |
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367 | */ |
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368 | mfc0 t0, C0_SR |
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369 | li t1,SR_IE /* Clear IE first (recommended) */ |
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370 | not t1 |
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371 | and t0,t1 |
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372 | mtc0 t0, C0_SR |
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373 | li t1,SR_EXL | SR_IE /* Set EXL and IE, this puts status register bits back to interrupted state */ |
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374 | or t0,t1 |
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375 | |
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376 | mtc0 t0, C0_SR |
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377 | NOP |
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378 | |
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379 | /* |
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380 | * prepare to get out of interrupt |
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381 | * return from interrupt (maybe to _ISR_Dispatch) |
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382 | * |
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383 | * LABEL "exit interrupt (simple case):" |
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384 | * prepare to get out of interrupt |
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385 | * return from interrupt |
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386 | */ |
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387 | |
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388 | _ISR_Handler_exit: |
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389 | |
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390 | /* restore interrupt context from stack */ |
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391 | LDREG t8, R_MDLO*R_SZ(sp) |
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392 | LDREG t0, R_T0*R_SZ(sp) |
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393 | mtlo t8 |
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394 | LDREG t8, R_MDHI*R_SZ(sp) |
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395 | LDREG t1, R_T1*R_SZ(sp) |
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396 | mthi t8 |
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397 | LDREG t2, R_T2*R_SZ(sp) |
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398 | LDREG t3, R_T3*R_SZ(sp) |
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399 | LDREG t4, R_T4*R_SZ(sp) |
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400 | LDREG t5, R_T5*R_SZ(sp) |
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401 | LDREG t6, R_T6*R_SZ(sp) |
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402 | LDREG t7, R_T7*R_SZ(sp) |
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403 | LDREG t8, R_T8*R_SZ(sp) |
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404 | LDREG t9, R_T9*R_SZ(sp) |
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405 | LDREG gp, R_GP*R_SZ(sp) |
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406 | LDREG fp, R_FP*R_SZ(sp) |
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407 | LDREG ra, R_RA*R_SZ(sp) |
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408 | LDREG a0, R_A0*R_SZ(sp) |
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409 | LDREG a1, R_A1*R_SZ(sp) |
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410 | LDREG a2, R_A2*R_SZ(sp) |
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411 | LDREG a3, R_A3*R_SZ(sp) |
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412 | LDREG v1, R_V1*R_SZ(sp) |
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413 | LDREG v0, R_V0*R_SZ(sp) |
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414 | |
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415 | LDREG k1, R_EPC*R_SZ(sp) |
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416 | mtc0 k1,C0_EPC |
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417 | |
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418 | .set noat |
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419 | LDREG AT, R_AT*R_SZ(sp) |
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420 | .set at |
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421 | |
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422 | ADDIU sp,sp,EXCP_STACK_SIZE |
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423 | |
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424 | _ISR_Handler_quick_exit: |
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425 | eret |
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426 | nop |
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427 | |
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428 | |
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429 | #if 0 |
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430 | .global int7_isr |
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431 | .extern Interrupt_7_isr |
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432 | int7_isr: |
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433 | /* Verify interrupt is from Timer */ |
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434 | la k0,IRCS /* read Interrupt Current Status register */ |
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435 | lw k0,(k0) |
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436 | nop /* reading from external device */ |
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437 | li k1,IRCS_CAUSE_MASK |
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438 | and k0,k0,k1 /* isolate interrupt cause */ |
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439 | |
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440 | li k1,INT7INT /* test for interrupt 7 */ |
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441 | subu k1,k0,k1 |
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442 | beq k1,zero,int7_isr1 |
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443 | nop |
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444 | j ra /* interrupt 7 no longer valid, return without doing anything */ |
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445 | nop |
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446 | int7_isr1: |
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447 | j Interrupt_7_isr /* Jump to Interrupt 7 isr */ |
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448 | nop |
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449 | #endif |
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450 | |
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451 | .set reorder |
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452 | |
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453 | ENDFRAME(rbtx4938_ISR_Handler) |
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454 | |
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455 | |
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456 | FRAME(_BRK_Handler,sp,0,ra) |
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457 | .set noreorder |
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458 | |
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459 | #ifdef USC |
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460 | la k0,INT_CFG3 /* Disable heartbeat interrupt in USC320, it interferes with PMON exception handler */ |
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461 | lw k1,(k0) |
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462 | li k0,~HBI_MASK |
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463 | and k1,k1,k0 |
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464 | la k0,INT_CFG3 |
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465 | sw k1,(k0) |
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466 | #endif |
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467 | |
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468 | la k0,_brk_esr_link /* Jump to next exception handler in PMON exception chain */ |
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469 | lw k0,(k0) |
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470 | lw k0,4(k0) |
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471 | j k0 |
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472 | nop |
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473 | |
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474 | .set reorder |
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475 | ENDFRAME(_BRK_Handler) |
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476 | |
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477 | |
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478 | /************************************************************************** |
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479 | ** |
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480 | ** init_exc_vecs() - moves the exception code into the addresses |
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481 | ** reserved for exception vectors |
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482 | ** |
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483 | ** UTLB Miss exception vector at address 0x80000000 |
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484 | ** |
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485 | ** General exception vector at address 0x80000080 |
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486 | ** |
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487 | ** RESET exception vector is at address 0xbfc00000 |
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488 | ** |
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489 | ***************************************************************************/ |
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490 | |
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491 | FRAME(init_exc_vecs,sp,0,ra) |
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492 | .set noreorder |
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493 | |
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494 | .extern mon_onintr |
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495 | |
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496 | /* Install interrupt handler in PMON exception handling chain */ |
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497 | |
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498 | addiu sp,sp,-8 |
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499 | sw ra,(sp) /* Save ra contents on stack */ |
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500 | move a0,zero |
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501 | la a1,_int_esr_link |
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502 | jal mon_onintr /* Make PMON system call to install interrupt exception handler */ |
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503 | nop |
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504 | li a0,9 |
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505 | la a1,_brk_esr_link |
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506 | jal mon_onintr /* Make PMON system call to install break exception handler */ |
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507 | nop |
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508 | lw ra,(sp) |
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509 | addiu sp,sp,8 /* Restore ra contents from stack */ |
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510 | j ra |
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511 | nop |
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512 | |
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513 | .set reorder |
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514 | ENDFRAME(init_exc_vecs) |
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515 | |
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516 | |
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517 | #if 0 /* Unused code below */ |
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518 | |
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519 | /************************************************************* |
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520 | * enable_int7(ints) |
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521 | * Enable interrupt 7 |
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522 | */ |
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523 | FRAME(enable_int7,sp,0,ra) |
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524 | .set noreorder |
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525 | |
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526 | la t0,IRDM1 # Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low) |
---|
527 | li t1,0x0 |
---|
528 | sw t1,(t0) |
---|
529 | |
---|
530 | la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2) |
---|
531 | li t1,0x200 |
---|
532 | sw t1,(t0) |
---|
533 | |
---|
534 | la t0,IRMSK # Set interrupt controller mask |
---|
535 | li t1,0x0 |
---|
536 | sw t1,(t0) |
---|
537 | |
---|
538 | la t0,IRDEN # Enable interrupts from controller |
---|
539 | li t1,0x1 |
---|
540 | sw t1,(t0) |
---|
541 | |
---|
542 | j ra |
---|
543 | nop |
---|
544 | .set reorder |
---|
545 | ENDFRAME(enable_int7) |
---|
546 | |
---|
547 | /************************************************************* |
---|
548 | * disable_int7(ints) |
---|
549 | * Disable interrupt 7 |
---|
550 | */ |
---|
551 | FRAME(disable_int7,sp,0,ra) |
---|
552 | .set noreorder |
---|
553 | |
---|
554 | la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 0 to diasble int 7) |
---|
555 | li t1,0x200 |
---|
556 | sw t1,(t0) |
---|
557 | |
---|
558 | j ra |
---|
559 | nop |
---|
560 | .set reorder |
---|
561 | ENDFRAME(disable_int7) |
---|
562 | |
---|
563 | #endif |
---|
564 | |
---|
565 | /************************************************************* |
---|
566 | * tx4938exception: |
---|
567 | * Diagnostic code that can be hooked to PMON interrupt handler. |
---|
568 | * Generates pulse on PIO22 pin. |
---|
569 | * Called from _exception code in PMON (see mips.s of PMON). |
---|
570 | * Return address is located in k1. |
---|
571 | */ |
---|
572 | FRAME(tx4938exception,sp,0,ra) |
---|
573 | .set noreorder |
---|
574 | la k0,k1tmp |
---|
575 | sw k1,(k0) |
---|
576 | |
---|
577 | /* Activate TX4938 PIO22 signal for diagnostics */ |
---|
578 | lui k0,0xff1f |
---|
579 | ori k0,k0,0xf500 |
---|
580 | lw k0,(k0) |
---|
581 | lui k1,0x40 |
---|
582 | or k1,k1,k0 |
---|
583 | lui k0,0xff1f |
---|
584 | ori k0,k0,0xf500 |
---|
585 | sw k1,(k0) |
---|
586 | nop |
---|
587 | |
---|
588 | /* De-activate TX4938 PIO22 signal for diagnostics */ |
---|
589 | lui k0,0xff1f |
---|
590 | ori k0,k0,0xf500 |
---|
591 | lw k0,(k0) |
---|
592 | lui k1,0x40 |
---|
593 | not k1 |
---|
594 | and k1,k1,k0 |
---|
595 | lui k0,0xff1f |
---|
596 | ori k0,k0,0xf500 |
---|
597 | sw k1,(k0) |
---|
598 | nop |
---|
599 | |
---|
600 | la k0,k1tmp |
---|
601 | lw k1,(k0) |
---|
602 | j k1 |
---|
603 | .set reorder |
---|
604 | ENDFRAME(tx4938exception) |
---|
605 | |
---|
606 | |
---|
607 | |
---|
608 | |
---|
609 | .data |
---|
610 | |
---|
611 | k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */ |
---|
612 | |
---|
613 | /************************************************************* |
---|
614 | * |
---|
615 | * Exception handler links, used in PMON exception handler chains |
---|
616 | */ |
---|
617 | /* Interrupt exception service routine link */ |
---|
618 | .global _int_esr_link |
---|
619 | _int_esr_link: |
---|
620 | .word 0 |
---|
621 | .word rbtx4938_ISR_Handler |
---|
622 | |
---|
623 | /* Break exception service routine link */ |
---|
624 | .global _brk_esr_link |
---|
625 | _brk_esr_link: |
---|
626 | .word 0 |
---|
627 | .word _BRK_Handler |
---|
628 | |
---|
629 | |
---|
630 | |
---|
631 | |
---|