source: rtems/c/src/lib/libbsp/mips/rbtx4938/clock/clockdrv.c @ f3b29236

Last change on this file since f3b29236 was f3b29236, checked in by Sebastian Huber <sebastian.huber@…>, on Sep 18, 2017 at 6:22:38 AM

bsps: Clock_driver_support_install_isr()

Remove old ISR parameter since is not used by the clock driver shell.
Make an implementation optional.

Update #3139.

  • Property mode set to 100644
File size: 4.0 KB
Line 
1/**
2 *  @file
3 * 
4 *  Instantiate the clock driver shell.
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#include <rtems.h>
17#include <bsp/irq.h>
18#include <bsp.h>
19
20#include <stdio.h>
21#include <stdlib.h>
22
23#include "yamon_api.h"
24
25
26/* #define CLOCK_DRIVER_USE_FAST_IDLE 1 */
27
28#define CLOCK_VECTOR TX4938_IRQ_TMR0
29
30#define TX4938_TIMER_INTERVAL_MODE 1
31
32#define TX4938_TIMER_MODE TX4938_TIMER_INTERVAL_MODE
33
34#if (TX4938_TIMER_MODE == TX4938_TIMER_INTERVAL_MODE)
35#define TX4938_TIMER_INTERRUPT_FLAG TIIS
36#define Clock_driver_support_initialize_hardware() \
37          Initialize_timer0_in_interval_mode()
38#else
39#error "Build Error: unsupported timer mode"
40#endif
41
42void new_brk_esr(void);
43
44t_yamon_retfunc esr_retfunc = 0;
45t_yamon_ref original_brk_esr = 0;
46t_yamon_ref original_tmr0_isr = 0;
47
48void new_brk_esr(void)
49{
50        if (original_tmr0_isr)
51        {
52                YAMON_FUNC_DEREGISTER_IC_ISR( original_tmr0_isr );
53                original_tmr0_isr = 0;
54        }
55        if (esr_retfunc)
56                esr_retfunc();
57}
58
59
60#define Clock_driver_support_install_isr( _new ) \
61  do { \
62    rtems_interrupt_handler_install( \
63      CLOCK_VECTOR, \
64      "clock", \
65      0, \
66      _new, \
67      NULL \
68    ); \
69    YAMON_FUNC_REGISTER_IC_ISR(17,(t_yamon_isr)_new,0,&original_tmr0_isr); /* Call Yamon to enable interrupt */ \
70  } while(0)
71
72
73#define Clock_driver_support_at_tick() \
74  do { \
75        uint32_t interrupt_flag; \
76        do { \
77                int loop_count; \
78                TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TISR, 0x0 ); /* Clear timer 0 interrupt */ \
79                loop_count = 0; \
80                do { /* Wait until interrupt flag is cleared (this prevents re-entering interrupt) */ \
81                        /* Read back interrupt status register and isolate interval timer flag */ \
82                        interrupt_flag = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TISR ) & TX4938_TIMER_INTERRUPT_FLAG; \
83                } while (interrupt_flag && (++loop_count < 10)); /* Loop while timer interrupt bit is set, or loop count is lees than 10 */ \
84        } while(interrupt_flag); \
85  } while(0)
86
87
88/* Setup timer in interval mode to generate peiodic interrupts */
89#define Initialize_timer0_in_interval_mode() \
90  do { \
91        uint32_t temp; \
92    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TCR, 0x0 ); /* Disable timer */ \
93    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \
94    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR, TIMER_CLEAR_ENABLE_MASK ); /* Set interval timer mode register */ \
95    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_CPRA, 0x3d090 ); /* Set tmier period ,10.0 msec (25 MHz timer clock) */ \
96    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TCR, 0xC0 ); /* Enable timer in interval mode */ \
97    temp = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR ); /* Enable interval timer interrupts */ \
98    temp |= TIMER_INT_ENABLE_MASK; \
99    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR, temp ); \
100  } while(0)
101
102
103
104#define Clock_driver_support_shutdown_hardware() \
105  do { \
106        uint32_t temp; \
107    temp = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR ); /* Disable interval timer interrupt */ \
108    temp &= ~TIMER_INT_ENABLE_MASK; \
109    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR, temp ); \
110    temp = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_PGMR ); /* Disable pulse generator interrupt */ \
111    temp &= ~(TPIAE | TPIBE); \
112    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_PGMR, temp ); \
113    TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TCR, 0x0 ); /* Disable timer */ \
114  } while(0)
115
116
117#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
118
119#include "../../../shared/clockdrv_shell.h"
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