1 | /** |
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2 | * @file |
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3 | * |
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4 | * Instantiate the clock driver shell. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 1989-2012. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #include <rtems.h> |
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17 | #include <bsp/irq.h> |
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18 | #include <bsp.h> |
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19 | |
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20 | /* #define CLOCK_DRIVER_USE_FAST_IDLE 1 */ |
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21 | |
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22 | #define CLOCK_VECTOR TX4925_IRQ_TMR0 |
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23 | |
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24 | #define TX4925_TIMER_INTERVAL_MODE 1 |
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25 | #define TX4925_TIMER_PULSE_MODE 2 |
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26 | #define TX4925_TIMER_MODE TX4925_TIMER_INTERVAL_MODE |
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27 | |
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28 | #if (TX4925_TIMER_MODE == TX4925_TIMER_INTERVAL_MODE) |
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29 | #define TX4925_TIMER_INTERRUPT_FLAG TIIS |
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30 | #define Clock_driver_support_initialize_hardware() \ |
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31 | Initialize_timer0_in_interval_mode() |
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32 | #elif (TX4925_TIMER_MODE == TX4925_TIMER_PULSE_MODE) |
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33 | #define TX4925_TIMER_INTERRUPT_FLAG TPIBS |
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34 | #define Clock_driver_support_initialize_hardware() \ |
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35 | Initialize_timer0_in_pulse_mode() |
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36 | #else |
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37 | #error "Build Error: need to select timer mode" |
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38 | #endif |
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39 | |
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40 | |
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41 | #define Clock_driver_support_install_isr( _new ) \ |
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42 | rtems_interrupt_handler_install( CLOCK_VECTOR, "clock", 0, _new, NULL ) |
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43 | |
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44 | |
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45 | #define Clock_driver_support_at_tick() \ |
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46 | do { \ |
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47 | uint32_t interrupt_flag; \ |
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48 | do { \ |
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49 | int loop_count; \ |
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50 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR, 0x0 ); /* Clear timer 0 interrupt */ \ |
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51 | loop_count = 0; \ |
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52 | do { /* Wait until interrupt flag is cleared (this prevents re-entering interrupt) */ \ |
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53 | /* Read back interrupt status register and isolate interval timer flag */ \ |
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54 | interrupt_flag = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR ) & TX4925_TIMER_INTERRUPT_FLAG; \ |
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55 | } while (interrupt_flag && (++loop_count < 10)); /* Loop while timer interrupt bit is set, or loop count is lees than 10 */ \ |
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56 | } while(interrupt_flag); \ |
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57 | } while(0) |
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58 | |
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59 | |
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60 | /* Setup timer in interval mode to generate peiodic interrupts */ |
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61 | #define Initialize_timer0_in_interval_mode() \ |
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62 | do { \ |
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63 | uint32_t temp; \ |
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64 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \ |
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65 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \ |
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66 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, TIMER_CLEAR_ENABLE_MASK ); /* Set interval timer mode register */ \ |
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67 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x30d40 ); /* Set tmier period ,10.0 msec (20 MHz timer clock) */ \ |
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68 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC0 ); /* Enable timer in interval mode */ \ |
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69 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 ); /* Set interrupt controller detection mode */ \ |
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70 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 ); /* Set interrupt controller level */ \ |
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71 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 ); /* Set interrupt controller mask */ \ |
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72 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 ); /* Enable interrupts from controller */ \ |
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73 | temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR ); /* Enable interval timer interrupts */ \ |
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74 | temp |= TIMER_INT_ENABLE_MASK; \ |
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75 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, temp ); \ |
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76 | } while(0) |
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77 | |
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78 | |
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79 | /* This mode is used to generate periodic interrupts and also output a pulse on PIO20 pin */ |
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80 | #define Initialize_timer0_in_pulse_mode() \ |
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81 | do { \ |
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82 | uint32_t temp; \ |
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83 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \ |
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84 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \ |
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85 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, FFI ); /* Set pulse generator mode register */ \ |
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86 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x3e8 ); /* Set pulse high duration ,0.05 msec (20 MHz timer clock) */ \ |
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87 | /* TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRB, 0x1388 ); */ /* Set pulse total period, 0.25 msec (20 MHz timer clock) */ \ |
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88 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRB, 0x30d40 ); /* Set pulse total period, 10 msec (20 MHz timer clock) */ \ |
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89 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC1 ); /* Enable timer in pulse generator mode */ \ |
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90 | \ |
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91 | /* Enable timer 0 output pulses on PIO20 */ \ |
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92 | temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_CFG_PCFG ); \ |
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93 | temp = (temp & ~ SELCHI) | SELTMR0; /* Enable timer 0 pulses on PIO20 */ \ |
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94 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_CFG_PCFG, temp ); \ |
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95 | \ |
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96 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 ); /* Set interrupt controller detection mode */ \ |
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97 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 ); /* Set interrupt controller level */ \ |
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98 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 ); /* Set interrupt controller mask */ \ |
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99 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 ); /* Enable interrupts from controller */ \ |
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100 | temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR ); /* Enable pulse generator interrupt */ \ |
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101 | temp |= TPIBE; /* Only want interrupts on B compare (where clock count is cleared) */ \ |
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102 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, temp ); \ |
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103 | } while(0) |
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104 | |
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105 | |
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106 | #define Clock_driver_support_shutdown_hardware() \ |
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107 | do { \ |
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108 | uint32_t temp; \ |
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109 | temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR ); /* Disable interval timer interrupt */ \ |
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110 | temp &= ~TIMER_INT_ENABLE_MASK; \ |
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111 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, temp ); \ |
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112 | temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR ); /* Disable pulse generator interrupt */ \ |
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113 | temp &= ~(TPIAE | TPIBE); \ |
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114 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, temp ); \ |
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115 | TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \ |
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116 | } while(0) |
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117 | |
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118 | #define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER |
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119 | |
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120 | #include "../../../shared/clockdrv_shell.h" |
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