source: rtems/c/src/lib/libbsp/mips/rbtx4925/clock/clockdrv.c @ 11978407

4.104.115
Last change on this file since 11978407 was 11978407, checked in by Ralf Corsepius <ralf.corsepius@…>, on 09/30/08 at 06:49:04

2008-09-30 Ralf Corsépius <ralf.corsepius@…>

  • clock/clockdrv.c: include "../../../shared/clockdrv_shell.h".
  • Makefile.am: Reflect changes above.
  • Property mode set to 100644
File size: 5.9 KB
Line 
1/*
2 *  Instantiate the clock driver shell.
3 *
4 *  clockdrv.c,v 1.5 2001/01/09 17:05:57 joel Exp
5 */
6
7#include <rtems.h>
8#include <libcpu/tx4925.h>
9#include <bsp.h>
10
11/* #define CLOCK_DRIVER_USE_FAST_IDLE */
12
13#define CLOCK_VECTOR TX4925_IRQ_TMR0
14
15#define TX4925_TIMER_INTERVAL_MODE 1
16#define TX4925_TIMER_PULSE_MODE 2
17#define TX4925_TIMER_MODE TX4925_TIMER_INTERVAL_MODE
18
19#if (TX4925_TIMER_MODE == TX4925_TIMER_INTERVAL_MODE)
20#define TX4925_TIMER_INTERRUPT_FLAG TIIS
21#define Clock_driver_support_initialize_hardware() \
22          Initialize_timer0_in_interval_mode()
23#elif (TX4925_TIMER_MODE == TX4925_TIMER_PULSE_MODE)
24#define TX4925_TIMER_INTERRUPT_FLAG TPIBS
25#define Clock_driver_support_initialize_hardware() \
26          Initialize_timer0_in_pulse_mode()
27#else
28#error "Build Error: need to select timer mode"
29#endif
30
31
32#define Clock_driver_support_install_isr( _new, _old ) \
33  do { \
34    _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
35  } while(0)
36
37
38#define Clock_driver_support_at_tick() \
39  do { \
40        uint32_t interrupt_flag; \
41        do { \
42                int loop_count; \
43                TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR, 0x0 ); /* Clear timer 0 interrupt */ \
44                loop_count = 0; \
45                do { /* Wait until interrupt flag is cleared (this prevents re-entering interrupt) */ \
46                        /* Read back interrupt status register and isolate interval timer flag */ \
47                        interrupt_flag = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR ) & TX4925_TIMER_INTERRUPT_FLAG; \
48                } while (interrupt_flag && (++loop_count < 10)); /* Loop while timer interrupt bit is set, or loop count is lees than 10 */ \
49        } while(interrupt_flag); \
50  } while(0)
51
52
53/* Setup timer in interval mode to generate peiodic interrupts */
54#define Initialize_timer0_in_interval_mode() \
55  do { \
56        uint32_t temp; \
57    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \
58    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \
59    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, TIMER_CLEAR_ENABLE_MASK ); /* Set interval timer mode register */ \
60    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x30d40 ); /* Set tmier period ,10.0 msec (20 MHz timer clock) */ \
61    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC0 ); /* Enable timer in interval mode */ \
62    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 ); /* Set interrupt controller detection mode */ \
63    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 ); /* Set interrupt controller level */ \
64    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 ); /* Set interrupt controller mask */ \
65    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 ); /* Enable interrupts from controller */ \
66    temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR ); /* Enable interval timer interrupts */ \
67    temp |= TIMER_INT_ENABLE_MASK; \
68    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, temp ); \
69  } while(0)
70
71
72/* This mode is used to generate periodic interrupts and also output a pulse on PIO20 pin */
73#define Initialize_timer0_in_pulse_mode() \
74  do { \
75        uint32_t temp; \
76    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \
77    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \
78    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, FFI ); /* Set pulse generator mode register */ \
79    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x3e8 ); /* Set pulse high duration ,0.05 msec (20 MHz timer clock) */ \
80/*    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRB, 0x1388 ); */ /* Set pulse total period, 0.25 msec (20 MHz timer clock) */ \
81    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRB, 0x30d40 ); /* Set pulse total period, 10 msec (20 MHz timer clock) */ \
82    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC1 ); /* Enable timer in pulse generator mode */ \
83 \
84        /* Enable timer 0 output pulses on PIO20 */ \
85    temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_CFG_PCFG ); \
86    temp = (temp & ~ SELCHI) | SELTMR0; /* Enable timer 0 pulses on PIO20 */ \
87    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_CFG_PCFG, temp ); \
88 \
89    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 ); /* Set interrupt controller detection mode */ \
90    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 ); /* Set interrupt controller level */ \
91    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 ); /* Set interrupt controller mask */ \
92    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 ); /* Enable interrupts from controller */ \
93    temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR ); /* Enable pulse generator interrupt */ \
94    temp |= TPIBE;      /* Only want interrupts on B compare (where clock count is cleared) */ \
95    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, temp ); \
96  } while(0)
97
98
99#define Clock_driver_support_shutdown_hardware() \
100  do { \
101        uint32_t temp; \
102    temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR ); /* Disable interval timer interrupt */ \
103    temp &= ~TIMER_INT_ENABLE_MASK; \
104    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, temp ); \
105    temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR ); /* Disable pulse generator interrupt */ \
106    temp &= ~(TPIAE | TPIBE); \
107    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, temp ); \
108    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \
109  } while(0)
110
111
112#include "../../../shared/clockdrv_shell.h"
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