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idtmem.S @ f05b2ac

4.104.114.84.95

Last change on this file since f05b2ac was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/21/04 at 16:01:48
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1	/*
2
3	Based upon IDT provided code with the following release:
4
5	This source code has been made available to you by IDT on an AS-IS
6	basis. Anyone receiving this source is licensed under IDT copyrights
7	to use it in any way he or she deems fit, including copying it,
8	modifying it, compiling it, and redistributing it either with or
9	without modifications. No license under IDT patents or patent
10	applications is to be implied by the copyright license.
11
12	Any user of this software should understand that IDT cannot provide
13	technical support for this software and will not be responsible for
14	any consequences resulting from the use of this software.
15
16	Any person who transfers this source code or any derivative work must
17	include the IDT copyright notice, this paragraph, and the preceeding
18	two paragraphs in the transferred software.
19
20	COPYRIGHT IDT CORPORATION 1996
21	LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22
23	$Id$
24
25	*/
26
27	/************************************************************************
28	**
29	** idtmem.s - memory and cache functions
30	**
31	** Copyright 1991 Integrated Device Technology, Inc.
32	** All Rights Reserved
33	**
34	**************************************************************************/
35
36	/*
37	* 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack
38	* to set mem_size.
39	*/
40
41	#include <rtems/mips/iregdef.h>
42	#include <rtems/mips/idtcpu.h>
43	#include <rtems/asm.h>
44
45	.data
46	mem_size:
47	.word 0
48	dcache_size:
49	.word 0
50	icache_size:
51	#if __mips == 1
52	.word MINCACHE
53	#endif
54	#if __mips == 3
55	.word 0
56	#endif
57
58	#if __mips == 3
59	.data
60	scache_size:
61	.word 0
62	icache_linesize:
63	.word 0
64	dcache_linesize:
65	.word 0
66	scache_linesize:
67	.word 0
68	#endif
69
70	.text
71
72	#if __mips == 1
73	#define CONFIGFRM ((2*4)+4)
74
75	/*************************************************************************
76	**
77	** Config_Dcache() -- determine size of Data cache
78	**
79	**************************************************************************/
80
81	FRAME(config_Dcache,sp, CONFIGFRM, ra)
82	.set noreorder
83	subu sp,CONFIGFRM
84	sw ra,CONFIGFRM-4(sp) /* save return address */
85	sw s0,44(sp) / save s0 in first regsave slot */
86	mfc0 s0,C0_SR /* save SR */
87	nop
88	mtc0 zero,C0_SR /* disable interrupts */
89	.set reorder
90	jal _size_cache /* returns Data cache size in v0 */
91	sw v0, dcache_size /* save it */
92	and s0, ~SR_PE /* do not clear PE */
93	.set noreorder
94	mtc0 s0,C0_SR /* restore SR */
95	nop
96	.set reorder
97	lw s0, 44(sp) / restore s0 */
98	lw ra,CONFIGFRM-4(sp) /* restore ra */
99	addu sp,CONFIGFRM /* pop stack */
100	j ra
101	ENDFRAME(config_Dcache)
102
103	/*************************************************************************
104	**
105	** Config_Icache() -- determine size of Instruction cache
106	** MUST be run in uncached mode/handled in idt_csu.s
107	**
108	**************************************************************************/
109
110	FRAME(config_Icache,sp, CONFIGFRM, ra)
111	.set noreorder
112	subu sp,CONFIGFRM
113	sw ra,CONFIGFRM-4(sp) /* save return address */
114	sw s0,44(sp) / save s0 in first regsave slot */
115	mfc0 s0,C0_SR /* save SR */
116	nop
117	mtc0 zero, C0_SR /* disable interrupts */
118	li v0,SR_SWC /* swap caches/disable ints */
119	mtc0 v0,C0_SR
120	nop
121	.set reorder
122	jal _size_cache /* returns instruction cache size */
123	.set noreorder
124	mtc0 zero,C0_SR /* swap back caches */
125	nop
126	and s0,~SR_PE /* do not inadvertantly clear PE */
127	mtc0 s0,C0_SR /* restore SR */
128	nop
129	.set reorder
130	sw v0, icache_size /* save it AFTER caches back */
131	lw s0,44(sp) / restore s0 */
132	lw ra,CONFIGFRM-4(sp) /* restore ra */
133	addu sp,CONFIGFRM /* pop stack */
134	j ra
135	ENDFRAME(config_Icache)
136
137	/************************************************************************
138	**
139	** _size_cache()
140	** returns cache size in v0
141	**
142	************************************************************************/
143
144	FRAME(_size_cache,sp,0,ra)
145	.set noreorder
146	mfc0 t0,C0_SR /* save current sr */
147	nop
148	and t0,~SR_PE /* do not inadvertently clear PE */
149	or v0,t0,SR_ISC /* isolate cache */
150	mtc0 v0,C0_SR
151	/*
152	* First check if there is a cache there at all
153	*/
154	move v0,zero
155	li v1,0xa5a5a5a5 /* distinctive pattern */
156	sw v1,K0BASE /* try to write into cache */
157	lw t1,K0BASE /* try to read from cache */
158	nop
159	mfc0 t2,C0_SR
160	nop
161	.set reorder
162	and t2,SR_CM
163	bne t2,zero,3f /* cache miss, must be no cache */
164	bne v1,t1,3f /* data not equal -> no cache */
165	/*
166	* Clear cache size boundries to known state.
167	*/
168	li v0,MINCACHE
169	1:
170	sw zero,K0BASE(v0)
171	sll v0,1
172	ble v0,MAXCACHE,1b
173
174	li v0,-1
175	sw v0,K0BASE(zero) /* store marker in cache */
176	li v0,MINCACHE /* MIN cache size */
177
178	2: lw v1,K0BASE(v0) /* Look for marker */
179	bne v1,zero,3f /* found marker */
180	sll v0,1 /* cache size * 2 */
181	ble v0,MAXCACHE,2b /* keep looking */
182	move v0,zero /* must be no cache */
183	.set noreorder
184	3: mtc0 t0,C0_SR /* restore sr */
185	j ra
186	nop
187	ENDFRAME(_size_cache)
188	.set reorder
189
190	#define FLUSHFRM (2*4)
191
192	/***************************************************************************
193	**
194	** flush_Dcache() - flush entire Data cache
195	**
196	****************************************************************************/
197	FRAME(flush_Dcache,sp,FLUSHFRM,ra)
198	lw t2, dcache_size
199	.set noreorder
200	mfc0 t3,C0_SR /* save SR */
201	nop
202	and t3,~SR_PE /* dont inadvertently clear PE */
203	beq t2,zero,_Dflush_done /* no D cache, get out! */
204	nop
205	li v0, SR_ISC /* isolate cache */
206	mtc0 v0, C0_SR
207	nop
208	.set reorder
209	li t0,K0BASE /* set loop registers */
210	or t1,t0,t2
211
212	2: sb zero,0(t0)
213	sb zero,4(t0)
214	sb zero,8(t0)
215	sb zero,12(t0)
216	sb zero,16(t0)
217	sb zero,20(t0)
218	sb zero,24(t0)
219	addu t0,32
220	sb zero,-4(t0)
221	bne t0,t1,2b
222
223	.set noreorder
224	_Dflush_done:
225	mtc0 t3,C0_SR /* restore Status Register */
226	.set reorder
227	j ra
228	ENDFRAME(flush_Dcache)
229
230	/***************************************************************************
231	**
232	** flush_Icache() - flush entire Instruction cache
233	**
234	** NOTE: Icache can only be flushed/cleared when uncached
235	** Code forces into uncached memory regardless of calling mode
236	**
237	****************************************************************************/
238	FRAME(flush_Icache,sp,FLUSHFRM,ra)
239	lw t1,icache_size
240	.set noreorder
241	mfc0 t3,C0_SR /* save SR */
242	nop
243	la v0,1f
244	li v1,K1BASE
245	or v0,v1
246	j v0 /* force into non-cached space */
247	nop
248	1:
249	and t3,~SR_PE /* dont inadvertently clear PE */
250	beq t1,zero,_Iflush_done /* no i-cache get out */
251	nop
252	li v0,SR_ISC\|SR_SWC /* disable intr, isolate and swap */
253	mtc0 v0,C0_SR
254	li t0,K0BASE
255	.set reorder
256	or t1,t0,t1
257
258	1: sb zero,0(t0)
259	sb zero,4(t0)
260	sb zero,8(t0)
261	sb zero,12(t0)
262	sb zero,16(t0)
263	sb zero,20(t0)
264	sb zero,24(t0)
265	addu t0,32
266	sb zero,-4(t0)
267	bne t0,t1,1b
268	.set noreorder
269	_Iflush_done:
270	mtc0 t3,C0_SR /* un-isolate, enable interrupts */
271	.set reorder
272	j ra
273	ENDFRAME(flush_Icache)
274
275	/**************************************************************************
276	**
277	** clear_Dcache(base_addr, byte_count) - flush portion of Data cache
278	**
279	** a0 = base address of portion to be cleared
280	** a1 = byte count of length
281	**
282	***************************************************************************/
283	FRAME(clear_Dcache,sp,0,ra)
284
285	lw t2, dcache_size /* Data cache size */
286	.set noreorder
287	mfc0 t3,C0_SR /* save SR */
288	nop
289	and t3,~SR_PE /* dont inadvertently clear PE */
290	nop
291	nop
292	.set reorder
293	/*
294	* flush data cache
295	*/
296
297	.set noreorder
298	nop
299	li v0,SR_ISC /* isolate data cache */
300	mtc0 v0,C0_SR
301	.set reorder
302	bltu t2,a1,1f /* cache is smaller than region */
303	move t2,a1
304	1: addu t2,a0 /* ending address + 1 */
305	move t0,a0
306
307	1: sb zero,0(t0)
308	sb zero,4(t0)
309	sb zero,8(t0)
310	sb zero,12(t0)
311	sb zero,16(t0)
312	sb zero,20(t0)
313	sb zero,24(t0)
314	addu t0,32
315	sb zero,-4(t0)
316	bltu t0,t2,1b
317
318	.set noreorder
319	mtc0 t3,C0_SR /* un-isolate, enable interrupts */
320	nop
321	.set reorder
322	j ra
323	ENDFRAME(clear_Dcache)
324
325	/**************************************************************************
326	**
327	** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache
328	**
329	** a0 = base address of portion to be cleared
330	** a1 = byte count of length
331	**
332	** NOTE: Icache can only be flushed/cleared when uncached
333	** Code forces into uncached memory regardless of calling mode
334	**
335	***************************************************************************/
336	FRAME(clear_Icache,sp,0,ra)
337
338	lw t1, icache_size /* Instruction cache size */
339	/*
340	* flush text cache
341	*/
342	.set noreorder
343	mfc0 t3,C0_SR /* save SR */
344	nop
345	la v0,1f
346	li v1,K1BASE
347	or v0,v1
348	j v0 /* force into non-cached space */
349	nop
350	1:
351	and t3,~SR_PE /* dont inadvertently clear PE */
352	nop
353	nop
354	li v0,SR_ISC\|SR_SWC /* disable intr, isolate and swap */
355	mtc0 v0,C0_SR
356	.set reorder
357	bltu t1,a1,1f /* cache is smaller than region */
358	move t1,a1
359	1: addu t1,a0 /* ending address + 1 */
360	move t0,a0
361
362	sb zero,0(t0)
363	sb zero,4(t0)
364	sb zero,8(t0)
365	sb zero,12(t0)
366	sb zero,16(t0)
367	sb zero,20(t0)
368	sb zero,24(t0)
369	addu t0,32
370	sb zero,-4(t0)
371	bltu t0,t1,1b
372	.set noreorder
373	mtc0 t3,C0_SR /* un-isolate, enable interrupts */
374	nop
375	nop
376	nop /* allow time for caches to swap */
377	.set reorder
378	j ra
379	ENDFRAME(clear_Icache)
380
381	/**************************************************************************
382	**
383	** get_mem_conf - get memory configuration
384	**
385	***************************************************************************/
386
387	FRAME(get_mem_conf,sp,0,ra)
388
389	lw t6, mem_size
390	sw t6, 0(a0)
391	lw t7, icache_size
392	sw t7, 4(a0)
393	lw t8, dcache_size
394	sw t8, 8(a0)
395	j ra
396
397	ENDFRAME(get_mem_conf)
398	#endif /* __mips == 1 */
399
400	#if __mips == 3
401	#define LEAF(label) FRAME(label,sp,0,ra)
402	#define XLEAF(label) \
403	.globl label ; \
404	label:
405	#define END(label) ENDFRAME(label)
406
407	/*
408	* cacheop macro to automate cache operations
409	* first some helpers...
410	*/
411	#define _mincache(size, maxsize) \
412	bltu size,maxsize,8f ; \
413	move size,maxsize ; \
414	8:
415
416	#define _align(tmp, minaddr, maxaddr, linesize) \
417	subu tmp,linesize,1 ; \
418	not tmp ; \
419	and minaddr,tmp ; \
420	addu maxaddr,-1 ; \
421	and maxaddr,tmp
422
423	/* This is a bit of a hack really because it relies on minaddr=a0 */
424	#define _doop1(op1) \
425	cache op1,0(a0)
426
427	#define _doop2(op1, op2) \
428	cache op1,0(a0) ; \
429	cache op2,0(a0)
430
431	/* specials for cache initialisation */
432	#define _doop1lw1(op1) \
433	cache op1,0(a0) ; \
434	lw zero,0(a0) ; \
435	cache op1,0(a0)
436
437	#define _doop121(op1,op2) \
438	cache op1,0(a0) ; \
439	nop; \
440	cache op2,0(a0) ; \
441	nop; \
442	cache op1,0(a0)
443
444	#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
445	.set noreorder ; \
446	7: _doop##tag##ops ; \
447	bne minaddr,maxaddr,7b ; \
448	addu minaddr,linesize ; \
449	.set reorder
450
451	/* finally the cache operation macros */
452	#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
453	_mincache(n, cache_size); \
454	blez n,9f ; \
455	addu n,kva ; \
456	_align(t1, kva, n, cache_linesize) ; \
457	_oploopn(kva, n, cache_linesize, tag, ops) ; \
458	9:
459
460	#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
461	blez n,9f ; \
462	addu n,kva ; \
463	_align(t1, kva, n, cache_linesize) ; \
464	_oploopn(kva, n, cache_linesize, tag, ops) ; \
465	9:
466
467	#define icacheop(kva, n, cache_size, cache_linesize, op) \
468	icacheopn(kva, n, cache_size, cache_linesize, 1, (op))
469
470	#define vcacheop(kva, n, cache_size, cache_linesize, op) \
471	vcacheopn(kva, n, cache_size, cache_linesize, 1, (op))
472
473	.text
474
475	/*
476	* static void _size_cache() R4000
477	*
478	* Internal routine to determine cache sizes by looking at R4000 config
479	* register. Sizes are returned in registers, as follows:
480	* t2 icache size
481	* t3 dcache size
482	* t6 scache size
483	* t4 icache line size
484	* t5 dcache line size
485	* t7 scache line size
486	*/
487	LEAF(_size_cache)
488	mfc0 t0,C0_CONFIG
489
490	and t1,t0,CFG_ICMASK
491	srl t1,CFG_ICSHIFT
492	li t2,0x1000
493	sll t2,t1
494
495	and t1,t0,CFG_DCMASK
496	srl t1,CFG_DCSHIFT
497	li t3,0x1000
498	sll t3,t1
499
500	li t4,32
501	and t1,t0,CFG_IB
502	bnez t1,1f
503	li t4,16
504	1:
505
506	li t5,32
507	and t1,t0,CFG_DB
508	bnez t1,1f
509	li t5,16
510	1:
511
512	move t6,zero # default to no scache
513	move t7,zero #
514
515	and t1,t0,CFG_C_UNCACHED # test config register
516	bnez t1,1f # no scache if uncached/non-coherent
517
518	li t6,0x100000 # assume 1Mb scache <<-NOTE
519	and t1,t0,CFG_SBMASK
520	srl t1,CFG_SBSHIFT
521	li t7,16
522	sll t7,t1
523	1: j ra
524	END(_size_cache)
525
526	/*
527	* void config_cache() R4000
528	*
529	* Work out size of I, D & S caches, assuming they are already initialised.
530	*/
531	LEAF(config_cache)
532	lw t0,icache_size
533	bgtz t0,8f # already known?
534	move v0,ra
535	bal _size_cache
536	move ra,v0
537
538	sw t2,icache_size
539	sw t3,dcache_size
540	sw t6,scache_size
541	sw t4,icache_linesize
542	sw t5,dcache_linesize
543	sw t7,scache_linesize
544	8: j ra
545	END(config_cache)
546
547	/*
548	* void _init_cache() R4000
549	*/
550	LEAF(_init_cache)
551	/*
552	* First work out the sizes
553	*/
554	move v0,ra
555	bal _size_cache
556	move ra,v0
557
558	/*
559	* The caches may be in an indeterminate state,
560	* so we force good parity into them by doing an
561	* invalidate, load/fill, invalidate for each line.
562	*/
563
564	/* disable all i/u and cache exceptions */
565	mfc0 v0,C0_SR
566	and v1,v0,~SR_IE
567	or v1,SR_DE
568	mtc0 v1,C0_SR
569
570	mtc0 zero,C0_TAGLO
571	mtc0 zero,C0_TAGHI
572
573	/* assume bottom of RAM will generate good parity for the cache */
574	li a0,PHYS_TO_K0(0)
575	move a2,t2 # icache_size
576	move a3,t4 # icache_linesize
577	move a1,a2
578	icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I))
579
580	li a0,PHYS_TO_K0(0)
581	move a2,t3 # dcache_size
582	move a3,t5 # dcache_linesize
583	move a1,a2
584	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D))
585
586	/* assume unified I & D in scache <<-NOTE */
587	blez t6,1f
588	li a0,PHYS_TO_K0(0)
589	move a2,t6
590	move a3,t7
591	move a1,a2
592	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD))
593
594	1: mtc0 v0,C0_SR
595	j ra
596	END(_init_cache)
597
598	/*
599	* void flush_cache (void) R4000
600	*
601	* Flush and invalidate all caches
602	*/
603	LEAF(flush_cache)
604	/* secondary cacheops do all the work if present */
605	lw a2,scache_size
606	blez a2,1f
607	lw a3,scache_linesize
608	li a0,PHYS_TO_K0(0)
609	move a1,a2
610	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
611	b 2f
612
613	1:
614	lw a2,icache_size
615	blez a2,2f
616	lw a3,icache_linesize
617	li a0,PHYS_TO_K0(0)
618	move a1,a2
619	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
620
621	lw a2,dcache_size
622	lw a3,dcache_linesize
623	li a0,PHYS_TO_K0(0)
624	move a1,a2
625	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
626
627	2: j ra
628	END(flush_cache)
629
630	/*
631	* void flush_cache_nowrite (void) R4000
632	*
633	* Invalidate all caches
634	*/
635	LEAF(flush_cache_nowrite)
636	mfc0 v0,C0_SR
637	and v1,v0,~SR_IE
638	mtc0 v1,C0_SR
639
640	mtc0 zero,C0_TAGLO
641	mtc0 zero,C0_TAGHI
642
643	lw a2,icache_size
644	blez a2,2f
645	lw a3,icache_linesize
646	li a0,PHYS_TO_K0(0)
647	move a1,a2
648	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
649
650	lw a2,dcache_size
651	lw a3,dcache_linesize
652	li a0,PHYS_TO_K0(0)
653	move a1,a2
654	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
655
656	lw a2,scache_size
657	blez a2,2f
658	lw a3,scache_linesize
659	li a0,PHYS_TO_K0(0)
660	move a1,a2
661	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
662
663	2: mtc0 v0,C0_SR
664	j ra
665	END(flush_cache_nowrite)
666
667	/*
668	* void clean_cache (unsigned kva, size_t n) R4000
669	*
670	* Writeback and invalidate address range in all caches
671	*/
672	LEAF(clean_cache)
673	XLEAF(clear_cache)
674
675	/* secondary cacheops do all the work (if fitted) */
676	lw a2,scache_size
677	blez a2,1f
678	lw a3,scache_linesize
679	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
680	b 2f
681
682	1: lw a2,icache_size
683	blez a2,2f
684	lw a3,icache_linesize
685	/* save kva & n for subsequent loop */
686	move t8,a0
687	move t9,a1
688	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
689
690	lw a2,dcache_size
691	lw a3,dcache_linesize
692	/* restore kva & n */
693	move a0,t8
694	move a1,t9
695	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
696
697	2: j ra
698	END(clean_cache)
699
700	/*
701	* void clean_dcache (unsigned kva, size_t n) R4000
702	*
703	* Writeback and invalidate address range in primary data cache
704	*/
705	LEAF(clean_dcache)
706	lw a2,dcache_size
707	blez a2,2f
708	lw a3,dcache_linesize
709
710	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
711
712	2: j ra
713	END(clean_dcache)
714
715	/*
716	* void clean_dcache_indexed (unsigned kva, size_t n) R4000
717	*
718	* Writeback and invalidate indexed range in primary data cache
719	*/
720	LEAF(clean_dcache_indexed)
721	lw a2,dcache_size
722	blez a2,2f
723	lw a3,dcache_linesize
724
725	#ifdef CPU_ORION
726	srl a2,1 # do one set (half cache) at a time
727	move t8,a0 # save kva & n
728	move t9,a1
729	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
730
731	addu a0,t8,a2 # do next set
732	move a1,t9 # restore n
733	#endif
734	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
735
736	2: j ra
737	END(clean_dcache_indexed)
738
739	/*
740	* void clean_dcache_nowrite (unsigned kva, size_t n) R4000
741	*
742	* Invalidate an address range in primary data cache
743	*/
744	LEAF(clean_dcache_nowrite)
745	lw a2,dcache_size
746	blez a2,2f
747	lw a3,dcache_linesize
748
749	vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
750
751	2: j ra
752	END(clean_dcache_nowrite)
753
754	/*
755	* void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000
756	*
757	* Invalidate indexed range in primary data cache
758	*/
759	LEAF(clean_dcache_nowrite_indexed)
760	mfc0 v0,C0_SR
761	and v1,v0,~SR_IE
762	mtc0 v1,C0_SR
763
764	mtc0 zero,C0_TAGLO
765	mtc0 zero,C0_TAGHI
766
767	lw a2,dcache_size
768	blez a2,2f
769	lw a3,dcache_linesize
770
771	#ifdef CPU_ORION
772	srl a2,1 # do one set (half cache) at a time
773	move t8,a0 # save kva & n
774	move t9,a1
775	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
776
777	addu a0,t8,a2 # do next set
778	move a1,t9 # restore n
779	#endif
780	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
781
782	2: mtc0 v0,C0_SR
783	j ra
784	END(clean_dcache_nowrite_indexed)
785
786	/*
787	* void clean_icache (unsigned kva, size_t n) R4000
788	*
789	* Invalidate address range in primary instruction cache
790	*/
791	LEAF(clean_icache)
792	lw a2,icache_size
793	blez a2,2f
794	lw a3,icache_linesize
795
796	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
797
798	2: j ra
799	END(clean_icache)
800
801	/*
802	* void clean_icache_indexed (unsigned kva, size_t n) R4000
803	*
804	* Invalidate indexed range in primary instruction cache
805	*/
806	LEAF(clean_icache_indexed)
807	lw a2,icache_size
808	blez a2,2f
809	lw a3,icache_linesize
810
811	#ifdef CPU_ORION
812	srl a2,1 # do one set (half cache) at a time
813	move t8,a0 # save kva & n
814	move t9,a1
815	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
816
817	addu a0,t8,a2 # do next set
818	move a1,t9 # restore n
819	#endif
820	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
821
822	2: j ra
823	END(clean_icache_indexed)
824
825	/*
826	* void clean_scache (unsigned kva, size_t n) R4000
827	*
828	* Writeback and invalidate address range in secondary cache
829	*/
830	LEAF(clean_scache)
831	lw a2,scache_size
832	blez a2,2f
833	lw a3,scache_linesize
834	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
835
836	2: j ra
837	END(clean_scache)
838
839	/*
840	* void clean_scache_indexed (unsigned kva, size_t n) R4000
841	*
842	* Writeback and invalidate indexed range in secondary cache
843	*/
844	LEAF(clean_scache_indexed)
845	lw a2,scache_size
846	blez a2,2f
847	lw a3,scache_linesize
848
849	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
850
851	2: j ra
852	END(clean_scache_indexed)
853
854	/*
855	* void clean_scache_nowrite (unsigned kva, size_t n) R4000
856	*
857	* Invalidate an address range in secondary cache
858	*/
859	LEAF(clean_scache_nowrite)
860	lw a2,scache_size
861	blez a2,2f
862	lw a3,scache_linesize
863
864	vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)
865
866	2: j ra
867	END(clean_scache_nowrite)
868
869	/*
870	* void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000
871	*
872	* Invalidate indexed range in secondary cache
873	*/
874	LEAF(clean_scache_nowrite_indexed)
875	mfc0 v0,C0_SR
876	and v1,v0,~SR_IE
877	mtc0 v1,C0_SR
878
879	mtc0 zero,C0_TAGLO
880	mtc0 zero,C0_TAGHI
881
882	lw a2,scache_size
883	blez a2,2f
884	lw a3,scache_linesize
885
886	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
887
888	2: mtc0 v0,C0_SR
889	j ra
890	END(clean_scache_nowrite_indexed)
891
892	/**************************************************************************
893	**
894	** get_mem_conf - get memory configuration R4000
895	**
896	***************************************************************************/
897
898	FRAME(get_mem_conf,sp,0,ra)
899
900	lw t6, mem_size
901	sw t6, 0(a0)
902	lw t7, icache_size
903	sw t7, 4(a0)
904	lw t8, dcache_size
905	sw t8, 8(a0)
906	lw t7, scache_size
907	sw t7, 12(a0)
908	j ra
909
910	ENDFRAME(get_mem_conf)
911
912	#endif /* __mips == 3 */
913
914	/*
915	* void set_mem_size (mem_size)
916	*
917	* config_memory()'s memory size gets written into mem_size here.
918	* Now we don't need to call config_cache() with memory size - New to IDTC6.0
919	*/
920	FRAME(set_memory_size,sp,0,ra)
921	sw a0, mem_size
922	j ra
923	ENDFRAME(set_memory_size)

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