[f198c63] | 1 | /* |
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| 2 | |
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| 3 | Based upon IDT provided code with the following release: |
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| 4 | |
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| 5 | This source code has been made available to you by IDT on an AS-IS |
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| 6 | basis. Anyone receiving this source is licensed under IDT copyrights |
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| 7 | to use it in any way he or she deems fit, including copying it, |
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| 8 | modifying it, compiling it, and redistributing it either with or |
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| 9 | without modifications. No license under IDT patents or patent |
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| 10 | applications is to be implied by the copyright license. |
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| 11 | |
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| 12 | Any user of this software should understand that IDT cannot provide |
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| 13 | technical support for this software and will not be responsible for |
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| 14 | any consequences resulting from the use of this software. |
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| 15 | |
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| 16 | Any person who transfers this source code or any derivative work must |
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| 17 | include the IDT copyright notice, this paragraph, and the preceeding |
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| 18 | two paragraphs in the transferred software. |
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| 19 | |
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| 20 | COPYRIGHT IDT CORPORATION 1996 |
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| 21 | LICENSED MATERIAL - PROGRAM PROPERTY OF IDT |
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| 22 | |
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| 23 | */ |
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| 24 | |
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| 25 | /************************************************************************ |
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| 26 | ** |
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| 27 | ** idtmem.s - memory and cache functions |
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| 28 | ** |
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| 29 | ** Copyright 1991 Integrated Device Technology, Inc. |
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| 30 | ** All Rights Reserved |
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| 31 | ** |
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| 32 | **************************************************************************/ |
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| 33 | |
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| 34 | /* |
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| 35 | * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack |
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| 36 | * to set mem_size. |
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| 37 | */ |
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| 38 | |
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| 39 | #include "iregdef.h" |
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| 40 | #include "idtcpu.h" |
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| 41 | #include "idtmon.h" |
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| 42 | #include "saunder.h" |
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| 43 | |
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| 44 | |
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| 45 | .data |
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| 46 | mem_size: |
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| 47 | .word 0 |
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| 48 | dcache_size: |
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| 49 | .word 0 |
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| 50 | icache_size: |
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| 51 | #if defined(CPU_R3000) |
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| 52 | .word MINCACHE |
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| 53 | #endif |
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| 54 | #if defined(CPU_R4000) |
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| 55 | .word 0 |
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| 56 | #endif |
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| 57 | |
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| 58 | #if defined(CPU_R4000) |
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| 59 | .data |
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| 60 | scache_size: |
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| 61 | .word 0 |
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| 62 | icache_linesize: |
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| 63 | .word 0 |
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| 64 | dcache_linesize: |
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| 65 | .word 0 |
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| 66 | scache_linesize: |
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| 67 | .word 0 |
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| 68 | #endif |
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| 69 | |
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| 70 | |
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| 71 | .text |
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| 72 | |
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| 73 | #if defined (CPU_R3000) |
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| 74 | #define CONFIGFRM ((2*4)+4) |
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| 75 | |
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| 76 | /************************************************************************* |
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| 77 | ** |
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| 78 | ** Config_Dcache() -- determine size of Data cache |
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| 79 | ** |
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| 80 | **************************************************************************/ |
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| 81 | |
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| 82 | FRAME(config_Dcache,sp, CONFIGFRM, ra) |
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| 83 | .set noreorder |
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| 84 | subu sp,CONFIGFRM |
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| 85 | sw ra,CONFIGFRM-4(sp) /* save return address */ |
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| 86 | sw s0,4*4(sp) /* save s0 in first regsave slot */ |
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| 87 | mfc0 s0,C0_SR /* save SR */ |
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| 88 | nop |
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| 89 | mtc0 zero,C0_SR /* disable interrupts */ |
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| 90 | .set reorder |
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| 91 | jal _size_cache /* returns Data cache size in v0 */ |
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| 92 | sw v0, dcache_size /* save it */ |
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| 93 | and s0, ~SR_PE /* do not clear PE */ |
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| 94 | .set noreorder |
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| 95 | mtc0 s0,C0_SR /* restore SR */ |
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| 96 | nop |
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| 97 | .set reorder |
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| 98 | lw s0, 4*4(sp) /* restore s0 */ |
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| 99 | lw ra,CONFIGFRM-4(sp) /* restore ra */ |
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| 100 | addu sp,CONFIGFRM /* pop stack */ |
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| 101 | j ra |
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| 102 | ENDFRAME(config_Dcache) |
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| 103 | |
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| 104 | |
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| 105 | /************************************************************************* |
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| 106 | ** |
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| 107 | ** Config_Icache() -- determine size of Instruction cache |
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| 108 | ** MUST be run in uncached mode/handled in idt_csu.s |
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| 109 | ** |
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| 110 | **************************************************************************/ |
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| 111 | |
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| 112 | FRAME(config_Icache,sp, CONFIGFRM, ra) |
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| 113 | .set noreorder |
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| 114 | subu sp,CONFIGFRM |
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| 115 | sw ra,CONFIGFRM-4(sp) /* save return address */ |
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| 116 | sw s0,4*4(sp) /* save s0 in first regsave slot */ |
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| 117 | mfc0 s0,C0_SR /* save SR */ |
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| 118 | nop |
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| 119 | mtc0 zero, C0_SR /* disable interrupts */ |
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| 120 | li v0,SR_SWC /* swap caches/disable ints */ |
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| 121 | mtc0 v0,C0_SR |
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| 122 | nop |
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| 123 | .set reorder |
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| 124 | jal _size_cache /* returns instruction cache size */ |
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| 125 | .set noreorder |
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| 126 | mtc0 zero,C0_SR /* swap back caches */ |
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| 127 | nop |
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| 128 | and s0,~SR_PE /* do not inadvertantly clear PE */ |
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| 129 | mtc0 s0,C0_SR /* restore SR */ |
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| 130 | nop |
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| 131 | .set reorder |
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| 132 | sw v0, icache_size /* save it AFTER caches back */ |
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| 133 | lw s0,4*4(sp) /* restore s0 */ |
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| 134 | lw ra,CONFIGFRM-4(sp) /* restore ra */ |
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| 135 | addu sp,CONFIGFRM /* pop stack */ |
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| 136 | j ra |
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| 137 | ENDFRAME(config_Icache) |
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| 138 | |
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| 139 | /************************************************************************ |
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| 140 | ** |
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| 141 | ** _size_cache() |
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| 142 | ** returns cache size in v0 |
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| 143 | ** |
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| 144 | ************************************************************************/ |
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| 145 | |
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| 146 | FRAME(_size_cache,sp,0,ra) |
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| 147 | .set noreorder |
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| 148 | mfc0 t0,C0_SR /* save current sr */ |
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| 149 | nop |
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| 150 | and t0,~SR_PE /* do not inadvertently clear PE */ |
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| 151 | or v0,t0,SR_ISC /* isolate cache */ |
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| 152 | mtc0 v0,C0_SR |
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| 153 | /* |
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| 154 | * First check if there is a cache there at all |
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| 155 | */ |
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| 156 | move v0,zero |
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| 157 | li v1,0xa5a5a5a5 /* distinctive pattern */ |
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| 158 | sw v1,K0BASE /* try to write into cache */ |
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| 159 | lw t1,K0BASE /* try to read from cache */ |
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| 160 | nop |
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| 161 | mfc0 t2,C0_SR |
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| 162 | nop |
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| 163 | .set reorder |
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| 164 | and t2,SR_CM |
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| 165 | bne t2,zero,3f /* cache miss, must be no cache */ |
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| 166 | bne v1,t1,3f /* data not equal -> no cache */ |
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| 167 | /* |
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| 168 | * Clear cache size boundries to known state. |
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| 169 | */ |
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| 170 | li v0,MINCACHE |
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| 171 | 1: |
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| 172 | sw zero,K0BASE(v0) |
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| 173 | sll v0,1 |
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| 174 | ble v0,MAXCACHE,1b |
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| 175 | |
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| 176 | li v0,-1 |
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| 177 | sw v0,K0BASE(zero) /* store marker in cache */ |
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| 178 | li v0,MINCACHE /* MIN cache size */ |
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| 179 | |
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| 180 | 2: lw v1,K0BASE(v0) /* Look for marker */ |
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| 181 | bne v1,zero,3f /* found marker */ |
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| 182 | sll v0,1 /* cache size * 2 */ |
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| 183 | ble v0,MAXCACHE,2b /* keep looking */ |
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| 184 | move v0,zero /* must be no cache */ |
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| 185 | .set noreorder |
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| 186 | 3: mtc0 t0,C0_SR /* restore sr */ |
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| 187 | j ra |
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| 188 | nop |
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| 189 | ENDFRAME(_size_cache) |
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| 190 | .set reorder |
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| 191 | |
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| 192 | |
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| 193 | #define FLUSHFRM (2*4) |
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| 194 | |
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| 195 | /*************************************************************************** |
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| 196 | ** |
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| 197 | ** flush_Dcache() - flush entire Data cache |
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| 198 | ** |
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| 199 | ****************************************************************************/ |
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| 200 | FRAME(flush_Dcache,sp,FLUSHFRM,ra) |
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| 201 | lw t2, dcache_size |
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| 202 | .set noreorder |
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| 203 | mfc0 t3,C0_SR /* save SR */ |
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| 204 | nop |
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| 205 | and t3,~SR_PE /* dont inadvertently clear PE */ |
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| 206 | beq t2,zero,_Dflush_done /* no D cache, get out! */ |
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| 207 | nop |
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| 208 | li v0, SR_ISC /* isolate cache */ |
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| 209 | mtc0 v0, C0_SR |
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| 210 | nop |
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| 211 | .set reorder |
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| 212 | li t0,K0BASE /* set loop registers */ |
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| 213 | or t1,t0,t2 |
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| 214 | |
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| 215 | 2: sb zero,0(t0) |
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| 216 | sb zero,4(t0) |
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| 217 | sb zero,8(t0) |
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| 218 | sb zero,12(t0) |
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| 219 | sb zero,16(t0) |
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| 220 | sb zero,20(t0) |
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| 221 | sb zero,24(t0) |
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| 222 | addu t0,32 |
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| 223 | sb zero,-4(t0) |
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| 224 | bne t0,t1,2b |
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| 225 | |
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| 226 | .set noreorder |
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| 227 | _Dflush_done: |
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| 228 | mtc0 t3,C0_SR /* restore Status Register */ |
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| 229 | .set reorder |
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| 230 | j ra |
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| 231 | ENDFRAME(flush_Dcache) |
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| 232 | |
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| 233 | |
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| 234 | /*************************************************************************** |
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| 235 | ** |
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| 236 | ** flush_Icache() - flush entire Instruction cache |
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| 237 | ** |
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| 238 | ** NOTE: Icache can only be flushed/cleared when uncached |
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| 239 | ** Code forces into uncached memory regardless of calling mode |
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| 240 | ** |
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| 241 | ****************************************************************************/ |
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| 242 | FRAME(flush_Icache,sp,FLUSHFRM,ra) |
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| 243 | lw t1,icache_size |
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| 244 | .set noreorder |
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| 245 | mfc0 t3,C0_SR /* save SR */ |
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| 246 | nop |
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| 247 | la v0,1f |
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| 248 | li v1,K1BASE |
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| 249 | or v0,v1 |
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| 250 | j v0 /* force into non-cached space */ |
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| 251 | nop |
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| 252 | 1: |
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| 253 | and t3,~SR_PE /* dont inadvertently clear PE */ |
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| 254 | beq t1,zero,_Iflush_done /* no i-cache get out */ |
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| 255 | nop |
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| 256 | li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */ |
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| 257 | mtc0 v0,C0_SR |
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| 258 | li t0,K0BASE |
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| 259 | .set reorder |
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| 260 | or t1,t0,t1 |
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| 261 | |
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| 262 | 1: sb zero,0(t0) |
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| 263 | sb zero,4(t0) |
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| 264 | sb zero,8(t0) |
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| 265 | sb zero,12(t0) |
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| 266 | sb zero,16(t0) |
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| 267 | sb zero,20(t0) |
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| 268 | sb zero,24(t0) |
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| 269 | addu t0,32 |
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| 270 | sb zero,-4(t0) |
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| 271 | bne t0,t1,1b |
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| 272 | .set noreorder |
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| 273 | _Iflush_done: |
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| 274 | mtc0 t3,C0_SR /* un-isolate, enable interrupts */ |
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| 275 | .set reorder |
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| 276 | j ra |
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| 277 | ENDFRAME(flush_Icache) |
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| 278 | |
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| 279 | /************************************************************************** |
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| 280 | ** |
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| 281 | ** clear_Dcache(base_addr, byte_count) - flush portion of Data cache |
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| 282 | ** |
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| 283 | ** a0 = base address of portion to be cleared |
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| 284 | ** a1 = byte count of length |
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| 285 | ** |
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| 286 | ***************************************************************************/ |
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| 287 | FRAME(clear_Dcache,sp,0,ra) |
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| 288 | |
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| 289 | lw t2, dcache_size /* Data cache size */ |
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| 290 | .set noreorder |
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| 291 | mfc0 t3,C0_SR /* save SR */ |
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| 292 | nop |
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| 293 | and t3,~SR_PE /* dont inadvertently clear PE */ |
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| 294 | nop |
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| 295 | nop |
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| 296 | .set reorder |
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| 297 | /* |
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| 298 | * flush data cache |
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| 299 | */ |
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| 300 | |
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| 301 | .set noreorder |
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| 302 | nop |
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| 303 | li v0,SR_ISC /* isolate data cache */ |
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| 304 | mtc0 v0,C0_SR |
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| 305 | .set reorder |
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| 306 | bltu t2,a1,1f /* cache is smaller than region */ |
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| 307 | move t2,a1 |
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| 308 | 1: addu t2,a0 /* ending address + 1 */ |
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| 309 | move t0,a0 |
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| 310 | |
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| 311 | 1: sb zero,0(t0) |
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| 312 | sb zero,4(t0) |
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| 313 | sb zero,8(t0) |
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| 314 | sb zero,12(t0) |
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| 315 | sb zero,16(t0) |
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| 316 | sb zero,20(t0) |
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| 317 | sb zero,24(t0) |
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| 318 | addu t0,32 |
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| 319 | sb zero,-4(t0) |
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| 320 | bltu t0,t2,1b |
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| 321 | |
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| 322 | .set noreorder |
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| 323 | mtc0 t3,C0_SR /* un-isolate, enable interrupts */ |
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| 324 | nop |
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| 325 | .set reorder |
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| 326 | j ra |
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| 327 | ENDFRAME(clear_Dcache) |
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| 328 | |
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| 329 | |
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| 330 | /************************************************************************** |
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| 331 | ** |
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| 332 | ** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache |
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| 333 | ** |
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| 334 | ** a0 = base address of portion to be cleared |
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| 335 | ** a1 = byte count of length |
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| 336 | ** |
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| 337 | ** NOTE: Icache can only be flushed/cleared when uncached |
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| 338 | ** Code forces into uncached memory regardless of calling mode |
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| 339 | ** |
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| 340 | ***************************************************************************/ |
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| 341 | FRAME(clear_Icache,sp,0,ra) |
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| 342 | |
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| 343 | lw t1, icache_size /* Instruction cache size */ |
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| 344 | /* |
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| 345 | * flush text cache |
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| 346 | */ |
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| 347 | .set noreorder |
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| 348 | mfc0 t3,C0_SR /* save SR */ |
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| 349 | nop |
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| 350 | la v0,1f |
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| 351 | li v1,K1BASE |
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| 352 | or v0,v1 |
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| 353 | j v0 /* force into non-cached space */ |
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| 354 | nop |
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| 355 | 1: |
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| 356 | and t3,~SR_PE /* dont inadvertently clear PE */ |
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| 357 | nop |
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| 358 | nop |
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| 359 | li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */ |
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| 360 | mtc0 v0,C0_SR |
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| 361 | .set reorder |
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| 362 | bltu t1,a1,1f /* cache is smaller than region */ |
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| 363 | move t1,a1 |
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| 364 | 1: addu t1,a0 /* ending address + 1 */ |
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| 365 | move t0,a0 |
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| 366 | |
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| 367 | sb zero,0(t0) |
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| 368 | sb zero,4(t0) |
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| 369 | sb zero,8(t0) |
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| 370 | sb zero,12(t0) |
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| 371 | sb zero,16(t0) |
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| 372 | sb zero,20(t0) |
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| 373 | sb zero,24(t0) |
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| 374 | addu t0,32 |
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| 375 | sb zero,-4(t0) |
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| 376 | bltu t0,t1,1b |
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| 377 | .set noreorder |
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| 378 | mtc0 t3,C0_SR /* un-isolate, enable interrupts */ |
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| 379 | nop |
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| 380 | nop |
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| 381 | nop /* allow time for caches to swap */ |
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| 382 | .set reorder |
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| 383 | j ra |
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| 384 | ENDFRAME(clear_Icache) |
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| 385 | |
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| 386 | |
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| 387 | /************************************************************************** |
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| 388 | ** |
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| 389 | ** get_mem_conf - get memory configuration |
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| 390 | ** |
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| 391 | ***************************************************************************/ |
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| 392 | |
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| 393 | |
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| 394 | FRAME(get_mem_conf,sp,0,ra) |
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| 395 | |
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| 396 | lw t6, mem_size |
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| 397 | sw t6, 0(a0) |
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| 398 | lw t7, icache_size |
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| 399 | sw t7, 4(a0) |
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| 400 | lw t8, dcache_size |
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| 401 | sw t8, 8(a0) |
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| 402 | j ra |
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| 403 | |
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| 404 | ENDFRAME(get_mem_conf) |
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| 405 | #endif /* defined CPU_R3000 */ |
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| 406 | |
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| 407 | #if defined(CPU_R4000) |
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| 408 | #define LEAF(label) FRAME(label,sp,0,ra) |
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| 409 | #define XLEAF(label) \ |
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| 410 | .globl label ; \ |
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| 411 | label: |
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| 412 | #define END(label) ENDFRAME(label) |
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| 413 | |
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| 414 | /* |
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| 415 | * cacheop macro to automate cache operations |
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| 416 | * first some helpers... |
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| 417 | */ |
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| 418 | #define _mincache(size, maxsize) \ |
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| 419 | bltu size,maxsize,8f ; \ |
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| 420 | move size,maxsize ; \ |
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| 421 | 8: |
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| 422 | |
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| 423 | #define _align(tmp, minaddr, maxaddr, linesize) \ |
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| 424 | subu tmp,linesize,1 ; \ |
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| 425 | not tmp ; \ |
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| 426 | and minaddr,tmp ; \ |
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| 427 | addu maxaddr,-1 ; \ |
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| 428 | and maxaddr,tmp |
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| 429 | |
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| 430 | /* This is a bit of a hack really because it relies on minaddr=a0 */ |
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| 431 | #define _doop1(op1) \ |
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| 432 | cache op1,0(a0) |
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| 433 | |
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| 434 | #define _doop2(op1, op2) \ |
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| 435 | cache op1,0(a0) ; \ |
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| 436 | cache op2,0(a0) |
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| 437 | |
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| 438 | /* specials for cache initialisation */ |
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| 439 | #define _doop1lw1(op1) \ |
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| 440 | cache op1,0(a0) ; \ |
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| 441 | lw zero,0(a0) ; \ |
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| 442 | cache op1,0(a0) |
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| 443 | |
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| 444 | #define _doop121(op1,op2) \ |
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| 445 | cache op1,0(a0) ; \ |
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| 446 | nop; \ |
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| 447 | cache op2,0(a0) ; \ |
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| 448 | nop; \ |
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| 449 | cache op1,0(a0) |
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| 450 | |
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| 451 | #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ |
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| 452 | .set noreorder ; \ |
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| 453 | 7: _doop##tag##ops ; \ |
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| 454 | bne minaddr,maxaddr,7b ; \ |
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| 455 | addu minaddr,linesize ; \ |
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| 456 | .set reorder |
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| 457 | |
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| 458 | /* finally the cache operation macros */ |
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| 459 | #define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \ |
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| 460 | _mincache(n, cache_size); \ |
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| 461 | blez n,9f ; \ |
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| 462 | addu n,kva ; \ |
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| 463 | _align(t1, kva, n, cache_linesize) ; \ |
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| 464 | _oploopn(kva, n, cache_linesize, tag, ops) ; \ |
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| 465 | 9: |
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| 466 | |
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| 467 | #define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \ |
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| 468 | blez n,9f ; \ |
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| 469 | addu n,kva ; \ |
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| 470 | _align(t1, kva, n, cache_linesize) ; \ |
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| 471 | _oploopn(kva, n, cache_linesize, tag, ops) ; \ |
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| 472 | 9: |
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| 473 | |
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| 474 | #define icacheop(kva, n, cache_size, cache_linesize, op) \ |
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| 475 | icacheopn(kva, n, cache_size, cache_linesize, 1, (op)) |
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| 476 | |
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| 477 | #define vcacheop(kva, n, cache_size, cache_linesize, op) \ |
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| 478 | vcacheopn(kva, n, cache_size, cache_linesize, 1, (op)) |
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| 479 | |
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| 480 | .text |
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| 481 | |
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| 482 | /* |
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| 483 | * static void _size_cache() R4000 |
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| 484 | * |
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| 485 | * Internal routine to determine cache sizes by looking at R4000 config |
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| 486 | * register. Sizes are returned in registers, as follows: |
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| 487 | * t2 icache size |
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| 488 | * t3 dcache size |
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| 489 | * t6 scache size |
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| 490 | * t4 icache line size |
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| 491 | * t5 dcache line size |
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| 492 | * t7 scache line size |
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| 493 | */ |
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| 494 | LEAF(_size_cache) |
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| 495 | mfc0 t0,C0_CONFIG |
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| 496 | |
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| 497 | and t1,t0,CFG_ICMASK |
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| 498 | srl t1,CFG_ICSHIFT |
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| 499 | li t2,0x1000 |
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| 500 | sll t2,t1 |
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| 501 | |
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| 502 | and t1,t0,CFG_DCMASK |
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| 503 | srl t1,CFG_DCSHIFT |
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| 504 | li t3,0x1000 |
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| 505 | sll t3,t1 |
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| 506 | |
---|
| 507 | li t4,32 |
---|
| 508 | and t1,t0,CFG_IB |
---|
| 509 | bnez t1,1f |
---|
| 510 | li t4,16 |
---|
| 511 | 1: |
---|
| 512 | |
---|
| 513 | li t5,32 |
---|
| 514 | and t1,t0,CFG_DB |
---|
| 515 | bnez t1,1f |
---|
| 516 | li t5,16 |
---|
| 517 | 1: |
---|
| 518 | |
---|
| 519 | move t6,zero # default to no scache |
---|
| 520 | move t7,zero # |
---|
| 521 | |
---|
| 522 | and t1,t0,CFG_C_UNCACHED # test config register |
---|
| 523 | bnez t1,1f # no scache if uncached/non-coherent |
---|
| 524 | |
---|
| 525 | li t6,0x100000 # assume 1Mb scache <<-NOTE |
---|
| 526 | and t1,t0,CFG_SBMASK |
---|
| 527 | srl t1,CFG_SBSHIFT |
---|
| 528 | li t7,16 |
---|
| 529 | sll t7,t1 |
---|
| 530 | 1: j ra |
---|
| 531 | END(_size_cache) |
---|
| 532 | |
---|
| 533 | |
---|
| 534 | /* |
---|
| 535 | * void config_cache() R4000 |
---|
| 536 | * |
---|
| 537 | * Work out size of I, D & S caches, assuming they are already initialised. |
---|
| 538 | */ |
---|
| 539 | LEAF(config_cache) |
---|
| 540 | lw t0,icache_size |
---|
| 541 | bgtz t0,8f # already known? |
---|
| 542 | move v0,ra |
---|
| 543 | bal _size_cache |
---|
| 544 | move ra,v0 |
---|
| 545 | |
---|
| 546 | sw t2,icache_size |
---|
| 547 | sw t3,dcache_size |
---|
| 548 | sw t6,scache_size |
---|
| 549 | sw t4,icache_linesize |
---|
| 550 | sw t5,dcache_linesize |
---|
| 551 | sw t7,scache_linesize |
---|
| 552 | 8: j ra |
---|
| 553 | END(config_cache) |
---|
| 554 | |
---|
| 555 | |
---|
| 556 | /* |
---|
| 557 | * void _init_cache() R4000 |
---|
| 558 | */ |
---|
| 559 | LEAF(_init_cache) |
---|
| 560 | /* |
---|
| 561 | * First work out the sizes |
---|
| 562 | */ |
---|
| 563 | move v0,ra |
---|
| 564 | bal _size_cache |
---|
| 565 | move ra,v0 |
---|
| 566 | |
---|
| 567 | /* |
---|
| 568 | * The caches may be in an indeterminate state, |
---|
| 569 | * so we force good parity into them by doing an |
---|
| 570 | * invalidate, load/fill, invalidate for each line. |
---|
| 571 | */ |
---|
| 572 | |
---|
| 573 | /* disable all i/u and cache exceptions */ |
---|
| 574 | mfc0 v0,C0_SR |
---|
| 575 | and v1,v0,~SR_IE |
---|
| 576 | or v1,SR_DE |
---|
| 577 | mtc0 v1,C0_SR |
---|
| 578 | |
---|
| 579 | mtc0 zero,C0_TAGLO |
---|
| 580 | mtc0 zero,C0_TAGHI |
---|
| 581 | |
---|
| 582 | /* assume bottom of RAM will generate good parity for the cache */ |
---|
| 583 | li a0,PHYS_TO_K0(0) |
---|
| 584 | move a2,t2 # icache_size |
---|
| 585 | move a3,t4 # icache_linesize |
---|
| 586 | move a1,a2 |
---|
| 587 | icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I)) |
---|
| 588 | |
---|
| 589 | li a0,PHYS_TO_K0(0) |
---|
| 590 | move a2,t3 # dcache_size |
---|
| 591 | move a3,t5 # dcache_linesize |
---|
| 592 | move a1,a2 |
---|
| 593 | icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D)) |
---|
| 594 | |
---|
| 595 | /* assume unified I & D in scache <<-NOTE */ |
---|
| 596 | blez t6,1f |
---|
| 597 | li a0,PHYS_TO_K0(0) |
---|
| 598 | move a2,t6 |
---|
| 599 | move a3,t7 |
---|
| 600 | move a1,a2 |
---|
| 601 | icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD)) |
---|
| 602 | |
---|
| 603 | 1: mtc0 v0,C0_SR |
---|
| 604 | j ra |
---|
| 605 | END(_init_cache) |
---|
| 606 | |
---|
| 607 | |
---|
| 608 | /* |
---|
| 609 | * void flush_cache (void) R4000 |
---|
| 610 | * |
---|
| 611 | * Flush and invalidate all caches |
---|
| 612 | */ |
---|
| 613 | LEAF(flush_cache) |
---|
| 614 | /* secondary cacheops do all the work if present */ |
---|
| 615 | lw a2,scache_size |
---|
| 616 | blez a2,1f |
---|
| 617 | lw a3,scache_linesize |
---|
| 618 | li a0,PHYS_TO_K0(0) |
---|
| 619 | move a1,a2 |
---|
| 620 | icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD) |
---|
| 621 | b 2f |
---|
| 622 | |
---|
| 623 | 1: |
---|
| 624 | lw a2,icache_size |
---|
| 625 | blez a2,2f |
---|
| 626 | lw a3,icache_linesize |
---|
| 627 | li a0,PHYS_TO_K0(0) |
---|
| 628 | move a1,a2 |
---|
| 629 | icacheop(a0,a1,a2,a3,Index_Invalidate_I) |
---|
| 630 | |
---|
| 631 | lw a2,dcache_size |
---|
| 632 | lw a3,dcache_linesize |
---|
| 633 | li a0,PHYS_TO_K0(0) |
---|
| 634 | move a1,a2 |
---|
| 635 | icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) |
---|
| 636 | |
---|
| 637 | 2: j ra |
---|
| 638 | END(flush_cache) |
---|
| 639 | |
---|
| 640 | /* |
---|
| 641 | * void flush_cache_nowrite (void) R4000 |
---|
| 642 | * |
---|
| 643 | * Invalidate all caches |
---|
| 644 | */ |
---|
| 645 | LEAF(flush_cache_nowrite) |
---|
| 646 | mfc0 v0,C0_SR |
---|
| 647 | and v1,v0,~SR_IE |
---|
| 648 | mtc0 v1,C0_SR |
---|
| 649 | |
---|
| 650 | mtc0 zero,C0_TAGLO |
---|
| 651 | mtc0 zero,C0_TAGHI |
---|
| 652 | |
---|
| 653 | lw a2,icache_size |
---|
| 654 | blez a2,2f |
---|
| 655 | lw a3,icache_linesize |
---|
| 656 | li a0,PHYS_TO_K0(0) |
---|
| 657 | move a1,a2 |
---|
| 658 | icacheop(a0,a1,a2,a3,Index_Invalidate_I) |
---|
| 659 | |
---|
| 660 | lw a2,dcache_size |
---|
| 661 | lw a3,dcache_linesize |
---|
| 662 | li a0,PHYS_TO_K0(0) |
---|
| 663 | move a1,a2 |
---|
| 664 | icacheop(a0,a1,a2,a3,Index_Store_Tag_D) |
---|
| 665 | |
---|
| 666 | lw a2,scache_size |
---|
| 667 | blez a2,2f |
---|
| 668 | lw a3,scache_linesize |
---|
| 669 | li a0,PHYS_TO_K0(0) |
---|
| 670 | move a1,a2 |
---|
| 671 | icacheop(a0,a1,a2,a3,Index_Store_Tag_SD) |
---|
| 672 | |
---|
| 673 | 2: mtc0 v0,C0_SR |
---|
| 674 | j ra |
---|
| 675 | END(flush_cache_nowrite) |
---|
| 676 | |
---|
| 677 | /* |
---|
| 678 | * void clean_cache (unsigned kva, size_t n) R4000 |
---|
| 679 | * |
---|
| 680 | * Writeback and invalidate address range in all caches |
---|
| 681 | */ |
---|
| 682 | LEAF(clean_cache) |
---|
| 683 | XLEAF(clear_cache) |
---|
| 684 | |
---|
| 685 | /* secondary cacheops do all the work (if fitted) */ |
---|
| 686 | lw a2,scache_size |
---|
| 687 | blez a2,1f |
---|
| 688 | lw a3,scache_linesize |
---|
| 689 | vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD) |
---|
| 690 | b 2f |
---|
| 691 | |
---|
| 692 | 1: lw a2,icache_size |
---|
| 693 | blez a2,2f |
---|
| 694 | lw a3,icache_linesize |
---|
| 695 | /* save kva & n for subsequent loop */ |
---|
| 696 | move t8,a0 |
---|
| 697 | move t9,a1 |
---|
| 698 | vcacheop(a0,a1,a2,a3,Hit_Invalidate_I) |
---|
| 699 | |
---|
| 700 | lw a2,dcache_size |
---|
| 701 | lw a3,dcache_linesize |
---|
| 702 | /* restore kva & n */ |
---|
| 703 | move a0,t8 |
---|
| 704 | move a1,t9 |
---|
| 705 | vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D) |
---|
| 706 | |
---|
| 707 | 2: j ra |
---|
| 708 | END(clean_cache) |
---|
| 709 | |
---|
| 710 | /* |
---|
| 711 | * void clean_dcache (unsigned kva, size_t n) R4000 |
---|
| 712 | * |
---|
| 713 | * Writeback and invalidate address range in primary data cache |
---|
| 714 | */ |
---|
| 715 | LEAF(clean_dcache) |
---|
| 716 | lw a2,dcache_size |
---|
| 717 | blez a2,2f |
---|
| 718 | lw a3,dcache_linesize |
---|
| 719 | |
---|
| 720 | vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D) |
---|
| 721 | |
---|
| 722 | 2: j ra |
---|
| 723 | END(clean_dcache) |
---|
| 724 | |
---|
| 725 | /* |
---|
| 726 | * void clean_dcache_indexed (unsigned kva, size_t n) R4000 |
---|
| 727 | * |
---|
| 728 | * Writeback and invalidate indexed range in primary data cache |
---|
| 729 | */ |
---|
| 730 | LEAF(clean_dcache_indexed) |
---|
| 731 | lw a2,dcache_size |
---|
| 732 | blez a2,2f |
---|
| 733 | lw a3,dcache_linesize |
---|
| 734 | |
---|
| 735 | #ifdef CPU_ORION |
---|
| 736 | srl a2,1 # do one set (half cache) at a time |
---|
| 737 | move t8,a0 # save kva & n |
---|
| 738 | move t9,a1 |
---|
| 739 | icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) |
---|
| 740 | |
---|
| 741 | addu a0,t8,a2 # do next set |
---|
| 742 | move a1,t9 # restore n |
---|
| 743 | #endif |
---|
| 744 | icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) |
---|
| 745 | |
---|
| 746 | 2: j ra |
---|
| 747 | END(clean_dcache_indexed) |
---|
| 748 | |
---|
| 749 | /* |
---|
| 750 | * void clean_dcache_nowrite (unsigned kva, size_t n) R4000 |
---|
| 751 | * |
---|
| 752 | * Invalidate an address range in primary data cache |
---|
| 753 | */ |
---|
| 754 | LEAF(clean_dcache_nowrite) |
---|
| 755 | lw a2,dcache_size |
---|
| 756 | blez a2,2f |
---|
| 757 | lw a3,dcache_linesize |
---|
| 758 | |
---|
| 759 | vcacheop(a0,a1,a2,a3,Hit_Invalidate_D) |
---|
| 760 | |
---|
| 761 | 2: j ra |
---|
| 762 | END(clean_dcache_nowrite) |
---|
| 763 | |
---|
| 764 | /* |
---|
| 765 | * void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000 |
---|
| 766 | * |
---|
| 767 | * Invalidate indexed range in primary data cache |
---|
| 768 | */ |
---|
| 769 | LEAF(clean_dcache_nowrite_indexed) |
---|
| 770 | mfc0 v0,C0_SR |
---|
| 771 | and v1,v0,~SR_IE |
---|
| 772 | mtc0 v1,C0_SR |
---|
| 773 | |
---|
| 774 | mtc0 zero,C0_TAGLO |
---|
| 775 | mtc0 zero,C0_TAGHI |
---|
| 776 | |
---|
| 777 | lw a2,dcache_size |
---|
| 778 | blez a2,2f |
---|
| 779 | lw a3,dcache_linesize |
---|
| 780 | |
---|
| 781 | #ifdef CPU_ORION |
---|
| 782 | srl a2,1 # do one set (half cache) at a time |
---|
| 783 | move t8,a0 # save kva & n |
---|
| 784 | move t9,a1 |
---|
| 785 | icacheop(a0,a1,a2,a3,Index_Store_Tag_D) |
---|
| 786 | |
---|
| 787 | addu a0,t8,a2 # do next set |
---|
| 788 | move a1,t9 # restore n |
---|
| 789 | #endif |
---|
| 790 | icacheop(a0,a1,a2,a3,Index_Store_Tag_D) |
---|
| 791 | |
---|
| 792 | 2: mtc0 v0,C0_SR |
---|
| 793 | j ra |
---|
| 794 | END(clean_dcache_nowrite_indexed) |
---|
| 795 | |
---|
| 796 | /* |
---|
| 797 | * void clean_icache (unsigned kva, size_t n) R4000 |
---|
| 798 | * |
---|
| 799 | * Invalidate address range in primary instruction cache |
---|
| 800 | */ |
---|
| 801 | LEAF(clean_icache) |
---|
| 802 | lw a2,icache_size |
---|
| 803 | blez a2,2f |
---|
| 804 | lw a3,icache_linesize |
---|
| 805 | |
---|
| 806 | vcacheop(a0,a1,a2,a3,Hit_Invalidate_I) |
---|
| 807 | |
---|
| 808 | 2: j ra |
---|
| 809 | END(clean_icache) |
---|
| 810 | |
---|
| 811 | /* |
---|
| 812 | * void clean_icache_indexed (unsigned kva, size_t n) R4000 |
---|
| 813 | * |
---|
| 814 | * Invalidate indexed range in primary instruction cache |
---|
| 815 | */ |
---|
| 816 | LEAF(clean_icache_indexed) |
---|
| 817 | lw a2,icache_size |
---|
| 818 | blez a2,2f |
---|
| 819 | lw a3,icache_linesize |
---|
| 820 | |
---|
| 821 | #ifdef CPU_ORION |
---|
| 822 | srl a2,1 # do one set (half cache) at a time |
---|
| 823 | move t8,a0 # save kva & n |
---|
| 824 | move t9,a1 |
---|
| 825 | icacheop(a0,a1,a2,a3,Index_Invalidate_I) |
---|
| 826 | |
---|
| 827 | addu a0,t8,a2 # do next set |
---|
| 828 | move a1,t9 # restore n |
---|
| 829 | #endif |
---|
| 830 | icacheop(a0,a1,a2,a3,Index_Invalidate_I) |
---|
| 831 | |
---|
| 832 | 2: j ra |
---|
| 833 | END(clean_icache_indexed) |
---|
| 834 | |
---|
| 835 | |
---|
| 836 | |
---|
| 837 | /* |
---|
| 838 | * void clean_scache (unsigned kva, size_t n) R4000 |
---|
| 839 | * |
---|
| 840 | * Writeback and invalidate address range in secondary cache |
---|
| 841 | */ |
---|
| 842 | LEAF(clean_scache) |
---|
| 843 | lw a2,scache_size |
---|
| 844 | blez a2,2f |
---|
| 845 | lw a3,scache_linesize |
---|
| 846 | vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD) |
---|
| 847 | |
---|
| 848 | 2: j ra |
---|
| 849 | END(clean_scache) |
---|
| 850 | |
---|
| 851 | /* |
---|
| 852 | * void clean_scache_indexed (unsigned kva, size_t n) R4000 |
---|
| 853 | * |
---|
| 854 | * Writeback and invalidate indexed range in secondary cache |
---|
| 855 | */ |
---|
| 856 | LEAF(clean_scache_indexed) |
---|
| 857 | lw a2,scache_size |
---|
| 858 | blez a2,2f |
---|
| 859 | lw a3,scache_linesize |
---|
| 860 | |
---|
| 861 | icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD) |
---|
| 862 | |
---|
| 863 | 2: j ra |
---|
| 864 | END(clean_scache_indexed) |
---|
| 865 | |
---|
| 866 | /* |
---|
| 867 | * void clean_scache_nowrite (unsigned kva, size_t n) R4000 |
---|
| 868 | * |
---|
| 869 | * Invalidate an address range in secondary cache |
---|
| 870 | */ |
---|
| 871 | LEAF(clean_scache_nowrite) |
---|
| 872 | lw a2,scache_size |
---|
| 873 | blez a2,2f |
---|
| 874 | lw a3,scache_linesize |
---|
| 875 | |
---|
| 876 | vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD) |
---|
| 877 | |
---|
| 878 | 2: j ra |
---|
| 879 | END(clean_scache_nowrite) |
---|
| 880 | |
---|
| 881 | /* |
---|
| 882 | * void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000 |
---|
| 883 | * |
---|
| 884 | * Invalidate indexed range in secondary cache |
---|
| 885 | */ |
---|
| 886 | LEAF(clean_scache_nowrite_indexed) |
---|
| 887 | mfc0 v0,C0_SR |
---|
| 888 | and v1,v0,~SR_IE |
---|
| 889 | mtc0 v1,C0_SR |
---|
| 890 | |
---|
| 891 | mtc0 zero,C0_TAGLO |
---|
| 892 | mtc0 zero,C0_TAGHI |
---|
| 893 | |
---|
| 894 | lw a2,scache_size |
---|
| 895 | blez a2,2f |
---|
| 896 | lw a3,scache_linesize |
---|
| 897 | |
---|
| 898 | icacheop(a0,a1,a2,a3,Index_Store_Tag_SD) |
---|
| 899 | |
---|
| 900 | 2: mtc0 v0,C0_SR |
---|
| 901 | j ra |
---|
| 902 | END(clean_scache_nowrite_indexed) |
---|
| 903 | |
---|
| 904 | /************************************************************************** |
---|
| 905 | ** |
---|
| 906 | ** get_mem_conf - get memory configuration R4000 |
---|
| 907 | ** |
---|
| 908 | ***************************************************************************/ |
---|
| 909 | |
---|
| 910 | |
---|
| 911 | FRAME(get_mem_conf,sp,0,ra) |
---|
| 912 | |
---|
| 913 | lw t6, mem_size |
---|
| 914 | sw t6, 0(a0) |
---|
| 915 | lw t7, icache_size |
---|
| 916 | sw t7, 4(a0) |
---|
| 917 | lw t8, dcache_size |
---|
| 918 | sw t8, 8(a0) |
---|
| 919 | lw t7, scache_size |
---|
| 920 | sw t7, 12(a0) |
---|
| 921 | j ra |
---|
| 922 | |
---|
| 923 | ENDFRAME(get_mem_conf) |
---|
| 924 | |
---|
| 925 | #endif /* defined(CPU_R4000) */ |
---|
| 926 | |
---|
| 927 | /* |
---|
| 928 | * void set_mem_size (mem_size) |
---|
| 929 | * |
---|
| 930 | * config_memory()'s memory size gets written into mem_size here. |
---|
| 931 | * Now we don't need to call config_cache() with memory size - New to IDTC6.0 |
---|
| 932 | */ |
---|
| 933 | FRAME(set_memory_size,sp,0,ra) |
---|
| 934 | sw a0, mem_size |
---|
| 935 | j ra |
---|
| 936 | ENDFRAME(set_memory_size) |
---|
| 937 | |
---|
| 938 | |
---|