source: rtems/c/src/lib/libbsp/mips/p4000/start/start.S @ f05b2ac

4.104.114.84.95
Last change on this file since f05b2ac was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/21/04 at 16:01:48

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1/*
2
3Based upon IDT provided code with the following release:
4
5This source code has been made available to you by IDT on an AS-IS
6basis. Anyone receiving this source is licensed under IDT copyrights
7to use it in any way he or she deems fit, including copying it,
8modifying it, compiling it, and redistributing it either with or
9without modifications.  No license under IDT patents or patent
10applications is to be implied by the copyright license.
11
12Any user of this software should understand that IDT cannot provide
13technical support for this software and will not be responsible for
14any consequences resulting from the use of this software.
15
16Any person who transfers this source code or any derivative work must
17include the IDT copyright notice, this paragraph, and the preceeding
18two paragraphs in the transferred software.
19
20COPYRIGHT IDT CORPORATION 1996
21LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22
23  $Id$
24*/
25
26/*************************************************************************
27**
28** Copyright 1991-95 Integrated Device Technology, Inc.
29**      All Rights Reserved
30**
31** idt_csu.S -- IDT stand alone startup code
32**
33**************************************************************************/
34#include <rtems/mips/iregdef.h>
35#include <rtems/mips/idtcpu.h>
36#include <rtems/asm.h>
37
38.extern _fbss,4           /* this is defined by the linker */
39.extern end,4             /* this is defined by the linker */
40
41.lcomm sim_mem_cfg_struct,12
42
43        .text
44
45#define TMP_STKSIZE  1024
46
47/**************************************************************************
48**
49**  start - Typicl standalone start up code required for R3000/R4000
50**
51**
52**      1)  Initialize the STATUS Register
53**              a) Clear parity error bit
54**              b) Set co_processor 1 usable bit ON
55**              c) Clear all IntMask Enables
56**              d) Set kernel/disabled mode
57**      2)  Initialize Cause Register
58**              a)  clear software interrupt bits
59**      3)  Determine FPU installed or not
60**              if not, clear CoProcessor 1 usable bit
61**      4)  Clear bss area
62**      5)  MUST allocate temporary stack until memory size determined
63**          It MUST be uncached to prevent overwriting when caches are cleared
64**      6)  Install exception handlers
65**      7)  Determine memory and cache sizes
66**      8)  Establish permanent stack (cached or uncached as defined by bss)
67**      9)  Flush Instruction and Data caches
68**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
69**      11)  Execute initialization code if the IDT/c library is to be used
70**
71**      12)  Jump to user's "main()" (boot_card() for RTEMS)
72**      13)  Jump to promexit
73**
74**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
75**      This is used to mark code specific to R3xxx or R4xxx processors.
76**      IDT/C 6.x defines __mips to be the ISA level for which we're
77**      generating code. This is used to make sure the stack etc. is
78**      double word aligned, when using -mips3 (default) or -mips2,
79**      when compiling with IDT/C6.x
80**
81***************************************************************************/
82
83FRAME(start,sp,0,ra)
84
85        .set    noreorder
86#ifdef _R3000
87        li      v0,SR_PE|SR_CU1        /* reset parity error and set */
88                                        /* cp1 usable */
89#endif
90#ifdef _R4000
91#if __mips==3 || defined(R4650)
92        li      v0,SR_CU1|SR_DE|SR_FR   /* initally clear ERL, enable FPA 64bit regs*/
93                                        /* 4650: Need fr to be set anyway */
94#else
95        li      v0,SR_CU1|SR_DE         /* initally clear ERL, enable FPA 32bit regs*/
96#endif /* mips3 */
97#endif
98
99        mtc0    v0,C0_SR                /* clr IntMsks/ kernel/disabled mode */
100        nop
101        mtc0    zero,C0_CAUSE           /* clear software interrupts */
102        nop
103
104#ifdef _R4000
105        li      v0,CFG_C_NONCOHERENT    # initialise default cache mode
106        mtc0    v0,C0_CONFIG
107#endif
108
109/*
110**      check to see if an fpu is really plugged in
111*/
112        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
113        mtc1    t3,fp0                  /* try to write them into fp0   */
114        mtc1    zero,fp1                /* try to write zero in fp      */
115        mfc1    t0,fp0
116        mfc1    t1,fp1
117        nop
118        bne     t0,t3,1f                /* branch if no match  */
119        nop
120        bne     t1,zero,1f              /* double check for positive id   */
121        nop
122        /* We have a FPU. clear fcsr */
123        ctc1    zero, fcr31
124        j       2f                      /* status register already correct  */
125        nop
1261:
127#ifdef _R3000
128        li      v0, SR_PE               /* reset parity error/NO cp1 usable */
129#endif
130
131#ifdef _R4000
132        li      v0,SR_DE                /* clear ERL and disable FPA */
133#endif
134
135        mtc0    v0, C0_SR               /* reset status register */
1362:
137        la      gp, _gp
138
139        la      v0,_fbss                /* clear bss before using it */
140        la      v1,end                  /* end of bss */
1413:      sw      zero,0(v0)
142        bltu    v0,v1,3b
143        add     v0,4
144
145/************************************************************************
146**
147**      Temporary Stack - needed to  handle stack saves until
148**                        memory size is determined and permanent stack set
149**
150**                        MUST be uncached to avoid confusion at cache
151**                             switching during memory sizing
152**
153*************************************************************************/
154#if __mips==3
155        /* For MIPS 3, we need to be sure that the stack is aligned on a
156         * double word boundary.
157         */
158        andi    t0, v0, 0x7
159        beqz    t0, 11f   /* Last three bits Zero, already aligned */
160        nop
161        add     v0, 4
16211:
163#endif
164
165        or      v0, K1BASE              /* switch to uncached */
166        add     v1, v0, TMP_STKSIZE     /* end of bss + length of tmp stack */
167        sub     v1, v1, (4*4)           /* overhead */
168        move    sp, v1                  /* set sp to top of stack */
1694:      sw      zero, 0(v0)
170        bltu    v0, v1, 4b              /* clear out temp stack */
171        add     v0, 4
172
173        jal     mips_install_isr_entries/* install exception handlers */
174        nop                             /* MUST do before memory probes */
175
176        la      v0, 5f
177        li      v1, K1BASE              /* force into uncached space */
178        or      v0, v1                  /* during memory/cache probes */
179        j       v0
180        nop
1815:
182        la      a0, sim_mem_cfg_struct
183        jal     sim_mem_cfg             /* Make SIM call to get mem size */
184        nop
185        la      a0, sim_mem_cfg_struct
186        lw      a0, 0(a0)               /* Get memory size from struct */
187#ifdef _R3000
188        jal     config_Icache
189        nop
190        jal     config_Dcache           /* determine size of D & I caches */
191        nop
192#endif
193#ifdef _R4000
194        jal     config_cache            /* determine size of D & I caches */
195        nop
196#endif
197
198        move    v0, a0                  /* mem_size */
199
200#if __mips==3
201        /* For MIPS 3, we need to be sure that the stack (and hence v0
202         * here) is aligned on a double word boundary.
203         */
204        andi    t0, v0, 0x7
205        beqz    t0, 12f   /* Last three bits Zero, already aligned */
206        nop
207        subu    v0, 4   /* mem_size was not aligned on doubleword bdry????*/
20812:
209#endif
210
211/*
212 * P_STACKSIZE is the size of the Prom Stack.
213 * the prom stack grows downward
214 */
215#define P_STACKSIZE     0x2000   /* sets stack size to 8k */
216
217/**************************************************************************
218**
219**  Permanent Stack - now know top of memory, put permanent stack there
220**
221***************************************************************************/
222
223        la      t2, _fbss               /* cache mode as linked */
224        and     t2, 0xF0000000          /* isolate segment */
225        la      t1, 6f
226        j       t1                      /* back to original cache mode */
227        nop
2286:
229        or      v0, t2                  /* stack back to original cache mode */
230        addiu   v0,v0,-16               /* overhead */
231        move    sp, v0                  /* now replace count w top of memory */
232        move    v1, v0
233        subu    v1, P_STACKSIZE         /* clear requested stack size */
234
2357:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
236        bltu    v1,v0,7b
237        add     v1, 4
238        .set    reorder
239
240#ifdef _R3000
241        jal     flush_Icache
242        jal     flush_Dcache            /* flush Data & Instruction caches */
243#endif
244#ifdef _R4000
245        jal     flush_cache_nowrite     /* flush Data & Instruction caches */
246#endif
247
248/**************************************************************************
249**
250**      If this chip supports a Translation Lookaside Buffer, clear it
251**
252***************************************************************************/
253
254        .set    noreorder
255        mfc0    t1,  C0_SR              /* look at Status Register */
256        nop
257        .set    reorder
258#ifdef _R3000
259        li      t2, SR_TS               /* TLB Shutdown bit */
260        and     t1,t2                   /* TLB Shutdown if 1 */
261        bnez    t1, 8f                  /* skip clearing if no TLB */
262#endif
263
264#ifndef R4650
265        jal     init_tlb                /* clear the tlb */
266#endif
267
268/************************************************************************
269**
270**  Initialization required if using IDT/c or libc.a, standard C Lib
271**
272**  can SKIP if not necessary for application
273**
274************************************************************************/
2758:
276
277        jal     idtsim_init_sbrk
278        jal     idtsim_init_file
279/***********************  END I/O initialization **********************/
280
281        jal     boot_card
282
283        jal     idtsim_promexit
284
285ENDFRAME(start)
286
287        .globl  sim_mem_cfg
288sim_mem_cfg:
289        .set noat
290        .set noreorder
291        li      AT, (0xbfc00000+((55)*8))
292        jr      AT
293        nop
294        .set at
295        .set reorder
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