1 | /* |
---|
2 | |
---|
3 | Based upon IDT provided code with the following release: |
---|
4 | |
---|
5 | This source code has been made available to you by IDT on an AS-IS |
---|
6 | basis. Anyone receiving this source is licensed under IDT copyrights |
---|
7 | to use it in any way he or she deems fit, including copying it, |
---|
8 | modifying it, compiling it, and redistributing it either with or |
---|
9 | without modifications. No license under IDT patents or patent |
---|
10 | applications is to be implied by the copyright license. |
---|
11 | |
---|
12 | Any user of this software should understand that IDT cannot provide |
---|
13 | technical support for this software and will not be responsible for |
---|
14 | any consequences resulting from the use of this software. |
---|
15 | |
---|
16 | Any person who transfers this source code or any derivative work must |
---|
17 | include the IDT copyright notice, this paragraph, and the preceeding |
---|
18 | two paragraphs in the transferred software. |
---|
19 | |
---|
20 | COPYRIGHT IDT CORPORATION 1996 |
---|
21 | LICENSED MATERIAL - PROGRAM PROPERTY OF IDT |
---|
22 | |
---|
23 | $Id$ |
---|
24 | */ |
---|
25 | |
---|
26 | /************************************************************************* |
---|
27 | ** |
---|
28 | ** Copyright 1991-95 Integrated Device Technology, Inc. |
---|
29 | ** All Rights Reserved |
---|
30 | ** |
---|
31 | ** idt_csu.S -- IDT stand alone startup code |
---|
32 | ** |
---|
33 | **************************************************************************/ |
---|
34 | #include <iregdef.h> |
---|
35 | #include <idtcpu.h> |
---|
36 | #include <asm.h> |
---|
37 | |
---|
38 | |
---|
39 | .extern _fbss,4 /* this is defined by the linker */ |
---|
40 | .extern end,4 /* this is defined by the linker */ |
---|
41 | |
---|
42 | .lcomm sim_mem_cfg_struct,12 |
---|
43 | |
---|
44 | .text |
---|
45 | |
---|
46 | |
---|
47 | #define TMP_STKSIZE 1024 |
---|
48 | |
---|
49 | /************************************************************************** |
---|
50 | ** |
---|
51 | ** start - Typicl standalone start up code required for R3000/R4000 |
---|
52 | ** |
---|
53 | ** |
---|
54 | ** 1) Initialize the STATUS Register |
---|
55 | ** a) Clear parity error bit |
---|
56 | ** b) Set co_processor 1 usable bit ON |
---|
57 | ** c) Clear all IntMask Enables |
---|
58 | ** d) Set kernel/disabled mode |
---|
59 | ** 2) Initialize Cause Register |
---|
60 | ** a) clear software interrupt bits |
---|
61 | ** 3) Determine FPU installed or not |
---|
62 | ** if not, clear CoProcessor 1 usable bit |
---|
63 | ** 4) Clear bss area |
---|
64 | ** 5) MUST allocate temporary stack until memory size determined |
---|
65 | ** It MUST be uncached to prevent overwriting when caches are cleared |
---|
66 | ** 6) Install exception handlers |
---|
67 | ** 7) Determine memory and cache sizes |
---|
68 | ** 8) Establish permanent stack (cached or uncached as defined by bss) |
---|
69 | ** 9) Flush Instruction and Data caches |
---|
70 | ** 10) If there is a Translation Lookaside Buffer, Clear the TLB |
---|
71 | ** 11) Execute initialization code if the IDT/c library is to be used |
---|
72 | ** |
---|
73 | ** 12) Jump to user's "main()" (boot_card() for RTEMS) |
---|
74 | ** 13) Jump to promexit |
---|
75 | ** |
---|
76 | ** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. |
---|
77 | ** This is used to mark code specific to R3xxx or R4xxx processors. |
---|
78 | ** IDT/C 6.x defines __mips to be the ISA level for which we're |
---|
79 | ** generating code. This is used to make sure the stack etc. is |
---|
80 | ** double word aligned, when using -mips3 (default) or -mips2, |
---|
81 | ** when compiling with IDT/C6.x |
---|
82 | ** |
---|
83 | ***************************************************************************/ |
---|
84 | |
---|
85 | FRAME(start,sp,0,ra) |
---|
86 | |
---|
87 | .set noreorder |
---|
88 | #ifdef _R3000 |
---|
89 | li v0,SR_PE|SR_CU1 /* reset parity error and set */ |
---|
90 | /* cp1 usable */ |
---|
91 | #endif |
---|
92 | #ifdef _R4000 |
---|
93 | #if __mips==3 || defined(R4650) |
---|
94 | li v0,SR_CU1|SR_DE|SR_FR /* initally clear ERL, enable FPA 64bit regs*/ |
---|
95 | /* 4650: Need fr to be set anyway */ |
---|
96 | #else |
---|
97 | li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPA 32bit regs*/ |
---|
98 | #endif /* mips3 */ |
---|
99 | #endif |
---|
100 | |
---|
101 | mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ |
---|
102 | nop |
---|
103 | mtc0 zero,C0_CAUSE /* clear software interrupts */ |
---|
104 | nop |
---|
105 | |
---|
106 | #ifdef _R4000 |
---|
107 | li v0,CFG_C_NONCOHERENT # initialise default cache mode |
---|
108 | mtc0 v0,C0_CONFIG |
---|
109 | #endif |
---|
110 | |
---|
111 | /* |
---|
112 | ** check to see if an fpu is really plugged in |
---|
113 | */ |
---|
114 | li t3,0xaaaa5555 /* put a's and 5's in t3 */ |
---|
115 | mtc1 t3,fp0 /* try to write them into fp0 */ |
---|
116 | mtc1 zero,fp1 /* try to write zero in fp */ |
---|
117 | mfc1 t0,fp0 |
---|
118 | mfc1 t1,fp1 |
---|
119 | nop |
---|
120 | bne t0,t3,1f /* branch if no match */ |
---|
121 | nop |
---|
122 | bne t1,zero,1f /* double check for positive id */ |
---|
123 | nop |
---|
124 | /* We have a FPU. clear fcsr */ |
---|
125 | ctc1 zero, fcr31 |
---|
126 | j 2f /* status register already correct */ |
---|
127 | nop |
---|
128 | 1: |
---|
129 | #ifdef _R3000 |
---|
130 | li v0, SR_PE /* reset parity error/NO cp1 usable */ |
---|
131 | #endif |
---|
132 | |
---|
133 | #ifdef _R4000 |
---|
134 | li v0,SR_DE /* clear ERL and disable FPA */ |
---|
135 | #endif |
---|
136 | |
---|
137 | mtc0 v0, C0_SR /* reset status register */ |
---|
138 | 2: |
---|
139 | la gp, _gp |
---|
140 | |
---|
141 | la v0,_fbss /* clear bss before using it */ |
---|
142 | la v1,end /* end of bss */ |
---|
143 | 3: sw zero,0(v0) |
---|
144 | bltu v0,v1,3b |
---|
145 | add v0,4 |
---|
146 | |
---|
147 | |
---|
148 | /************************************************************************ |
---|
149 | ** |
---|
150 | ** Temporary Stack - needed to handle stack saves until |
---|
151 | ** memory size is determined and permanent stack set |
---|
152 | ** |
---|
153 | ** MUST be uncached to avoid confusion at cache |
---|
154 | ** switching during memory sizing |
---|
155 | ** |
---|
156 | *************************************************************************/ |
---|
157 | #if __mips==3 |
---|
158 | /* For MIPS 3, we need to be sure that the stack is aligned on a |
---|
159 | * double word boundary. |
---|
160 | */ |
---|
161 | andi t0, v0, 0x7 |
---|
162 | beqz t0, 11f /* Last three bits Zero, already aligned */ |
---|
163 | nop |
---|
164 | add v0, 4 |
---|
165 | 11: |
---|
166 | #endif |
---|
167 | |
---|
168 | or v0, K1BASE /* switch to uncached */ |
---|
169 | add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ |
---|
170 | sub v1, v1, (4*4) /* overhead */ |
---|
171 | move sp, v1 /* set sp to top of stack */ |
---|
172 | 4: sw zero, 0(v0) |
---|
173 | bltu v0, v1, 4b /* clear out temp stack */ |
---|
174 | add v0, 4 |
---|
175 | |
---|
176 | jal mips_install_isr_entries/* install exception handlers */ |
---|
177 | nop /* MUST do before memory probes */ |
---|
178 | |
---|
179 | la v0, 5f |
---|
180 | li v1, K1BASE /* force into uncached space */ |
---|
181 | or v0, v1 /* during memory/cache probes */ |
---|
182 | j v0 |
---|
183 | nop |
---|
184 | 5: |
---|
185 | la a0, sim_mem_cfg_struct |
---|
186 | jal sim_mem_cfg /* Make SIM call to get mem size */ |
---|
187 | nop |
---|
188 | la a0, sim_mem_cfg_struct |
---|
189 | lw a0, 0(a0) /* Get memory size from struct */ |
---|
190 | #ifdef _R3000 |
---|
191 | jal config_Icache |
---|
192 | nop |
---|
193 | jal config_Dcache /* determine size of D & I caches */ |
---|
194 | nop |
---|
195 | #endif |
---|
196 | #ifdef _R4000 |
---|
197 | jal config_cache /* determine size of D & I caches */ |
---|
198 | nop |
---|
199 | #endif |
---|
200 | |
---|
201 | move v0, a0 /* mem_size */ |
---|
202 | |
---|
203 | #if __mips==3 |
---|
204 | /* For MIPS 3, we need to be sure that the stack (and hence v0 |
---|
205 | * here) is aligned on a double word boundary. |
---|
206 | */ |
---|
207 | andi t0, v0, 0x7 |
---|
208 | beqz t0, 12f /* Last three bits Zero, already aligned */ |
---|
209 | nop |
---|
210 | subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ |
---|
211 | 12: |
---|
212 | #endif |
---|
213 | |
---|
214 | |
---|
215 | /* |
---|
216 | * P_STACKSIZE is the size of the Prom Stack. |
---|
217 | * the prom stack grows downward |
---|
218 | */ |
---|
219 | #define P_STACKSIZE 0x2000 /* sets stack size to 8k */ |
---|
220 | |
---|
221 | |
---|
222 | /************************************************************************** |
---|
223 | ** |
---|
224 | ** Permanent Stack - now know top of memory, put permanent stack there |
---|
225 | ** |
---|
226 | ***************************************************************************/ |
---|
227 | |
---|
228 | la t2, _fbss /* cache mode as linked */ |
---|
229 | and t2, 0xF0000000 /* isolate segment */ |
---|
230 | la t1, 6f |
---|
231 | j t1 /* back to original cache mode */ |
---|
232 | nop |
---|
233 | 6: |
---|
234 | or v0, t2 /* stack back to original cache mode */ |
---|
235 | addiu v0,v0,-16 /* overhead */ |
---|
236 | move sp, v0 /* now replace count w top of memory */ |
---|
237 | move v1, v0 |
---|
238 | subu v1, P_STACKSIZE /* clear requested stack size */ |
---|
239 | |
---|
240 | 7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ |
---|
241 | bltu v1,v0,7b |
---|
242 | add v1, 4 |
---|
243 | .set reorder |
---|
244 | |
---|
245 | #ifdef _R3000 |
---|
246 | jal flush_Icache |
---|
247 | jal flush_Dcache /* flush Data & Instruction caches */ |
---|
248 | #endif |
---|
249 | #ifdef _R4000 |
---|
250 | jal flush_cache_nowrite /* flush Data & Instruction caches */ |
---|
251 | #endif |
---|
252 | |
---|
253 | |
---|
254 | |
---|
255 | /************************************************************************** |
---|
256 | ** |
---|
257 | ** If this chip supports a Translation Lookaside Buffer, clear it |
---|
258 | ** |
---|
259 | ***************************************************************************/ |
---|
260 | |
---|
261 | .set noreorder |
---|
262 | mfc0 t1, C0_SR /* look at Status Register */ |
---|
263 | nop |
---|
264 | .set reorder |
---|
265 | #ifdef _R3000 |
---|
266 | li t2, SR_TS /* TLB Shutdown bit */ |
---|
267 | and t1,t2 /* TLB Shutdown if 1 */ |
---|
268 | bnez t1, 8f /* skip clearing if no TLB */ |
---|
269 | #endif |
---|
270 | |
---|
271 | #ifndef R4650 |
---|
272 | jal init_tlb /* clear the tlb */ |
---|
273 | #endif |
---|
274 | |
---|
275 | |
---|
276 | /************************************************************************ |
---|
277 | ** |
---|
278 | ** Initialization required if using IDT/c or libc.a, standard C Lib |
---|
279 | ** |
---|
280 | ** can SKIP if not necessary for application |
---|
281 | ** |
---|
282 | ************************************************************************/ |
---|
283 | 8: |
---|
284 | |
---|
285 | jal idtsim_init_sbrk |
---|
286 | jal idtsim_init_file |
---|
287 | /*********************** END I/O initialization **********************/ |
---|
288 | |
---|
289 | |
---|
290 | jal boot_card |
---|
291 | |
---|
292 | jal idtsim_promexit |
---|
293 | |
---|
294 | ENDFRAME(start) |
---|
295 | |
---|
296 | |
---|
297 | .globl sim_mem_cfg |
---|
298 | sim_mem_cfg: |
---|
299 | .set noat |
---|
300 | .set noreorder |
---|
301 | li AT, (0xbfc00000+((55)*8)) |
---|
302 | jr AT |
---|
303 | nop |
---|
304 | .set at |
---|
305 | .set reorder |
---|