1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @ingroup bsp_interrupt |
---|
5 | * |
---|
6 | * @brief Malta Interrupt Definitions |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * COPYRIGHT (c) 1989-2012. |
---|
11 | * On-Line Applications Research Corporation (OAR). |
---|
12 | * |
---|
13 | * The license and distribution terms for this file may be |
---|
14 | * found in the file LICENSE in this distribution or at |
---|
15 | * http://www.rtems.org/license/LICENSE. |
---|
16 | */ |
---|
17 | |
---|
18 | #ifndef LIBBSP_MIPS_MALTA_IRQ_H |
---|
19 | #define LIBBSP_MIPS_MALTA_IRQ_H |
---|
20 | |
---|
21 | #ifndef ASM |
---|
22 | #include <rtems.h> |
---|
23 | #include <rtems/irq.h> |
---|
24 | #include <rtems/irq-extension.h> |
---|
25 | #include <rtems/score/mips.h> |
---|
26 | #endif |
---|
27 | |
---|
28 | /** |
---|
29 | * @addtogroup bsp_interrupt |
---|
30 | * |
---|
31 | * @{ |
---|
32 | */ |
---|
33 | |
---|
34 | #define BSP_INTERRUPT_VECTOR_MIN 0 |
---|
35 | |
---|
36 | /* |
---|
37 | * Interrupt Vector Numbers |
---|
38 | * |
---|
39 | * NOTE: Numbers 0-15 directly map to levels on the IRC. |
---|
40 | * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. |
---|
41 | */ |
---|
42 | #define MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0 |
---|
43 | #define MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0 |
---|
44 | #define MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1 |
---|
45 | #define MALTA_CPU_INT0 MALTA_CPU_INT_START+2 |
---|
46 | #define MALTA_CPU_INT1 MALTA_CPU_INT_START+3 |
---|
47 | #define MALTA_CPU_INT2 MALTA_CPU_INT_START+4 |
---|
48 | #define MALTA_CPU_INT3 MALTA_CPU_INT_START+5 |
---|
49 | #define MALTA_CPU_INT4 MALTA_CPU_INT_START+6 |
---|
50 | #define MALTA_CPU_INT5 MALTA_CPU_INT_START+7 |
---|
51 | #define MALTA_CPU_INT_LAST MALTA_CPU_INT5 |
---|
52 | |
---|
53 | #define MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1 |
---|
54 | #define MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0 |
---|
55 | #define MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1 |
---|
56 | #define MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2 |
---|
57 | #define MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3 |
---|
58 | #define MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4 |
---|
59 | #define MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5 |
---|
60 | #define MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6 |
---|
61 | #define MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7 |
---|
62 | #define MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8 |
---|
63 | #define MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9 |
---|
64 | #define MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10 |
---|
65 | #define MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11 |
---|
66 | #define MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12 |
---|
67 | #define MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13 |
---|
68 | #define MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14 |
---|
69 | #define MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15 |
---|
70 | #define MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15 |
---|
71 | |
---|
72 | #define MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1 |
---|
73 | #define MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0 |
---|
74 | #define MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1 |
---|
75 | #define MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2 |
---|
76 | #define MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3 |
---|
77 | #define MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4 |
---|
78 | #define MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5 |
---|
79 | #define MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6 |
---|
80 | #define MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7 |
---|
81 | #define MALTA_PCI_ADP_LAST MALTA_PCI_ADP31 |
---|
82 | # |
---|
83 | |
---|
84 | #define BSP_INTERRUPT_VECTOR_MAX MALTA_PCI_ADP_LAST |
---|
85 | |
---|
86 | /* |
---|
87 | * Redefine interrupts with more descriptive names. |
---|
88 | * The Generic ones above match the hardware name, |
---|
89 | * where these match the device name. |
---|
90 | */ |
---|
91 | #define MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0 |
---|
92 | #define MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1 |
---|
93 | #define MALTA_INT_TTY2 MALTA_CPU_INT2 |
---|
94 | #define MALTA_INT_COREHI MALTA_CPU_INT3 |
---|
95 | #define MALTA_INT_CORELO MALTA_CPU_INT4 |
---|
96 | #define MALTA_INT_TICKER MALTA_CPU_INT5 |
---|
97 | |
---|
98 | #define MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0 |
---|
99 | #define MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1 |
---|
100 | #define MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2 |
---|
101 | #define MALTA_IRQ_TTY1 MALTA_SB_IRQ_3 |
---|
102 | #define MALTA_IRQ_TTY0 MALTA_SB_IRQ_4 |
---|
103 | #define MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5 |
---|
104 | #define MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6 |
---|
105 | #define MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7 |
---|
106 | #define MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8 |
---|
107 | #define MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9 |
---|
108 | /* PCI A, PCI B (including Ethernet) PCI slot 1..4, Ethernet */ |
---|
109 | #define MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10 |
---|
110 | /* PCI slot 1..4 (audio, USB) */ |
---|
111 | #define MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11 |
---|
112 | #define MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12 |
---|
113 | #define MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13 |
---|
114 | #define MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14 |
---|
115 | #define MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15 |
---|
116 | #define MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20 |
---|
117 | #define MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B |
---|
118 | #define MALTA_IRQ_AUDIO MALTA_PCI_ADP22 |
---|
119 | #define MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27 |
---|
120 | #define MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28 |
---|
121 | #define MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29 |
---|
122 | #define MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30 |
---|
123 | #define MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31 |
---|
124 | |
---|
125 | #ifndef ASM |
---|
126 | |
---|
127 | #endif /* ASM */ |
---|
128 | |
---|
129 | /** @} */ |
---|
130 | |
---|
131 | #endif /* LIBBSP_MIPS_MALTA_IRQ_H */ |
---|