1 | /** |
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2 | * @file |
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3 | * |
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4 | * This include file contains some definitions specific to the |
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5 | * MIPS Malta Board. |
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6 | */ |
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7 | |
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8 | /* |
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9 | * COPYRIGHT (c) 1989-2012. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/license/LICENSE. |
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15 | */ |
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16 | |
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17 | #ifndef LIBBSP_MIPS_MALTA_BSP_H |
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18 | #define LIBBSP_MIPS_MALTA_BSP_H |
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19 | |
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20 | #ifndef ASM |
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21 | |
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22 | #include <bspopts.h> |
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23 | #include <bsp/default-initial-extension.h> |
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24 | |
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25 | #include <rtems.h> |
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26 | |
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27 | #ifdef __cplusplus |
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28 | extern "C" { |
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29 | #endif |
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30 | |
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31 | #define BSP_FEATURE_IRQ_EXTENSION |
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32 | #define BSP_SHARED_HANDLER_SUPPORT 1 |
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33 | |
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34 | #define REVISION_REGISTER_ADDRESS 0x1fc00010 |
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35 | #define PRORV_MASK 0x0000000f /* 4 bit Product Revision */ |
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36 | #define PROID_MASK 0x000000f0 /* 4 bit Product ID */ |
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37 | #define CORRV_MASK 0x00000300 /* 2 bit Core Board Revision */ |
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38 | #define CORID_MASK 0x0000fc00 /* 6 bit Core Board ID */ |
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39 | #define FPGRV_MASK 0x00ff0000 /* 8 bit CBUS FPGA Revision */ |
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40 | #define BSP_8259_BASE_ADDRESS (0x18000000UL | 0xa0000000UL) |
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41 | #define BSP_PCI_BASE_ADDRESS (0x1be00000UL | 0xa0000000UL) |
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42 | #define BSP_NIC_IO_BASE (0x10000000UL | 0xa0000000UL) |
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43 | #define PCI0_IO_BASE (0x18000000UL | 0xa0000000UL) |
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44 | #define BSP_NIC_MEM_BASE (0x00000000UL | 0xa0000000UL) |
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45 | |
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46 | /* functions */ |
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47 | #define WRITE_PROTECTED_UINT8( _addr, _value ) \ |
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48 | do { \ |
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49 | volatile uint8_t *_ptr = _addr | 0x80000000; \ |
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50 | *_ptr = _value; \ |
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51 | } |
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52 | #define WRITE_PROTECTED_UINT16( _addr, _value ) \ |
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53 | do { \ |
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54 | volatile uint16_t *_ptr = _addr | 0x80000000; \ |
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55 | *_ptr = _value; \ |
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56 | } |
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57 | #define WRITE_PROTECTED_UINT32( _addr, _value ) \ |
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58 | do { \ |
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59 | volatile uint32_t *_ptr = _addr | 0x80000000; \ |
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60 | *_ptr = _value; \ |
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61 | } |
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62 | #define READ_PROTECTED_UINT8( _addr, _value ) \ |
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63 | do { \ |
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64 | volatile uint8_t *_ptr = _addr | 0x80000000; \ |
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65 | _value = *_ptr; \ |
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66 | } |
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67 | #define READ_PROTECTED_UINT16( _addr, _value ) \ |
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68 | do { \ |
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69 | volatile uint16_t *_ptr = _addr | 0x80000000; \ |
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70 | _value = *_ptr; \ |
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71 | } |
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72 | #define READ_PROTECTED_UINT32( _addr, _value ) \ |
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73 | do { \ |
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74 | volatile uint32_t *_ptr = _addr | 0x80000000; \ |
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75 | _value = *_ptr; \ |
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76 | } |
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77 | |
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78 | #define READ_UINT8( _register_, _value_ ) \ |
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79 | ((_value_) = *((volatile unsigned char *)(_register_))) |
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80 | |
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81 | #define WRITE_UINT8( _register_, _value_ ) \ |
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82 | (*((volatile unsigned char *)(_register_)) = (_value_)) |
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83 | |
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84 | #define READ_UINT16( _register_, _value_ ) \ |
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85 | ((_value_) = *((volatile unsigned short *)(_register_))) |
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86 | |
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87 | #define WRITE_UINT16( _register_, _value_ ) \ |
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88 | (*((volatile unsigned short *)(_register_)) = (_value_)) |
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89 | |
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90 | void simple_out_32(uint32_t base, uint32_t addr, uint32_t val); |
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91 | void simple_out_le32(uint32_t base, uint32_t addr, uint32_t val); |
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92 | uint8_t simple_in_8( uint32_t base, uint32_t addr ); |
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93 | void simple_out_8( uint32_t base, uint32_t addr, uint8_t val ); |
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94 | int16_t simple_in_le16( uint32_t base, uint32_t addr ); |
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95 | int16_t simple_in_16( uint32_t base, uint32_t addr ); |
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96 | uint32_t simple_in_le32( uint32_t base, uint32_t addr ); |
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97 | uint32_t simple_in_32( uint32_t base, uint32_t addr ); |
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98 | void simple_out_le16( uint32_t base, uint32_t addr, uint16_t val ); |
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99 | void simple_out_16( uint32_t base, uint32_t addr, uint16_t val ); |
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100 | |
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101 | /* |
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102 | * Prototypes for methods called from .S for dependency tracking |
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103 | */ |
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104 | void init_tlb(void); |
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105 | void resettlb(int i); |
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106 | |
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107 | #ifdef __cplusplus |
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108 | } |
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109 | #endif |
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110 | |
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111 | #endif /* !ASM */ |
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112 | |
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113 | #endif |
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