source: rtems/c/src/lib/libbsp/mips/jmr3904/start/regs.h @ 0436cfb

4.9.2
Last change on this file since 0436cfb was 0436cfb, checked in by cvs2git <rtems-devel@…>, on Sep 15, 2009 at 5:32:54 AM

This commit was manufactured by cvs2svn to create tag 'rtems-4-9-2'.

Sprout from rtems-4-9-branch 2009-03-12 17:03:39 UTC Joel Sherrill <joel.sherrill@…> 'Upgrade to 4.9.2'
Cherrypick from rtems-4-9-branch 2009-09-15 05:32:51 UTC cvs2git <rtems-devel@…> 'This commit was manufactured by cvs2svn to create branch 'rtems-4-9-branch'.':

c/src/lib/libbsp/arm/gba/console/defaultfont.h
c/src/lib/libbsp/arm/smdk2410/include/.cvsignore
c/src/lib/libbsp/bare/preinstall.am
c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore
c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore
c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore
c/src/lib/libbsp/mips/csb350/start/regs.h
c/src/lib/libbsp/mips/genmongoosev/start/regs.h
c/src/lib/libbsp/mips/hurricane/liblnk/regs.h
c/src/lib/libbsp/mips/jmr3904/start/regs.h
c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h
c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h
c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore
c/src/lib/libbsp/powerpc/virtex/include/.cvsignore

  • Property mode set to 100644
File size: 5.3 KB
RevLine 
[0436cfb]1/*
2 * regs.S -- standard MIPS register names from
3 * newlib-1.8.2/libgloss/mips and adapted.
4 *
5 * Copyright (c) 1995 Cygnus Support
6 *
7 * The authors hereby grant permission to use, copy, modify, distribute,
8 * and license this software and its documentation for any purpose, provided
9 * that existing copyright notices are retained in all copies and that this
10 * notice is included verbatim in any distributions. No written agreement,
11 * license, or royalty fee is required for any of the authorized uses.
12 * Modifications to this software may be copyrighted by their authors
13 * and need not follow the licensing terms described here, provided that
14 * the new terms are clearly indicated on the first page of each file where
15 * they apply.
16 */
17
18/* Standard MIPS register names: */
19#define zero    $0
20#define z0      $0
21#define v0      $2
22#define v1      $3
23#define a0      $4
24#define a1      $5
25#define a2      $6
26#define a3      $7
27#define t0      $8
28#define t1      $9
29#define t2      $10
30#define t3      $11
31#define t4      $12
32#define t5      $13
33#define t6      $14
34#define t7      $15
35#define s0      $16
36#define s1      $17
37#define s2      $18
38#define s3      $19
39#define s4      $20
40#define s5      $21
41#define s6      $22
42#define s7      $23
43#define t8      $24
44#define t9      $25
45#define k0      $26     /* kernel private register 0 */
46#define k1      $27     /* kernel private register 1 */
47#define gp      $28     /* global data pointer */
48#define sp      $29     /* stack-pointer */
49#define fp      $30     /* frame-pointer */
50#define ra      $31     /* return address */
51#define pc      $pc     /* pc, used on mips16 */
52
53#define fp0     $f0
54#define fp1     $f1
55
56/* Useful memory constants: */
57#define K0BASE          0x80000000
58#ifndef __mips64
59#define K1BASE          0xA0000000
60#else
61#define K1BASE          0xFFFFFFFFA0000000LL
62#endif
63
64#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
65
66/* Standard Co-Processor 0 register numbers: */
67#define C0_COUNT        $9              /* Count Register */
68#define C0_SR           $12             /* Status Register */
69#define C0_CAUSE        $13             /* last exception description */
70#define C0_EPC          $14             /* Exception error address */
71#define C0_CONFIG       $16             /* CPU configuration */
72
73/* Standard Status Register bitmasks: */
74#define SR_CU1          0x20000000      /* Mark CP1 as usable */
75#define SR_FR           0x04000000      /* Enable MIPS III FP registers */
76#define SR_BEV          0x00400000      /* Controls location of exception vectors */
77#define SR_PE           0x00100000      /* Mark soft reset (clear parity error) */
78
79#define SR_KX           0x00000080      /* Kernel extended addressing enabled */
80#define SR_SX           0x00000040      /* Supervisor extended addressing enabled */
81#define SR_UX           0x00000020      /* User extended addressing enabled */
82
83/* Standard (R4000) cache operations. Taken from "MIPS R4000
84   Microprocessor User's Manual" 2nd edition: */
85
86#define CACHE_I         (0)     /* primary instruction */
87#define CACHE_D         (1)     /* primary data */
88#define CACHE_SI        (2)     /* secondary instruction */
89#define CACHE_SD        (3)     /* secondary data (or combined instruction/data) */
90
91#define INDEX_INVALIDATE                (0)     /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
92#define INDEX_LOAD_TAG                  (1)
93#define INDEX_STORE_TAG                 (2)
94#define CREATE_DIRTY_EXCLUSIVE          (3)     /* CACHE_D and CACHE_SD only */
95#define HIT_INVALIDATE                  (4)
96#define CACHE_FILL                      (5)     /* CACHE_I only */
97#define HIT_WRITEBACK_INVALIDATE        (5)     /* CACHE_D and CACHE_SD only */
98#define HIT_WRITEBACK                   (6)     /* CACHE_I, CACHE_D and CACHE_SD only */
99#define HIT_SET_VIRTUAL                 (7)     /* CACHE_SI and CACHE_SD only */
100
101#define BUILD_CACHE_OP(o,c)             (((o) << 2) | (c))
102
103/* Individual cache operations: */
104#define INDEX_INVALIDATE_I              BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
105#define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
106#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
107#define INDEX_WRITEBACK_INVALIDATE_SD   BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
108
109#define INDEX_LOAD_TAG_I                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
110#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
111#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
112#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
113
114#define INDEX_STORE_TAG_I               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
115#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
116#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
117#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
118
119#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
120#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
121
122#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
123#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
124#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
125#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
126
127#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
128#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
129#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
130
131#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
132#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
133#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
134
135#define HIT_SET_VIRTUAL_SI              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
136#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
137
138/*> EOF regs.S <*/
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