| 1 | /* |
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| 2 | |
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| 3 | Based upon IDT provided code with the following release: |
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| 4 | |
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| 5 | This source code has been made available to you by IDT on an AS-IS |
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| 6 | basis. Anyone receiving this source is licensed under IDT copyrights |
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| 7 | to use it in any way he or she deems fit, including copying it, |
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| 8 | modifying it, compiling it, and redistributing it either with or |
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| 9 | without modifications. No license under IDT patents or patent |
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| 10 | applications is to be implied by the copyright license. |
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| 11 | |
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| 12 | Any user of this software should understand that IDT cannot provide |
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| 13 | technical support for this software and will not be responsible for |
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| 14 | any consequences resulting from the use of this software. |
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| 15 | |
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| 16 | Any person who transfers this source code or any derivative work must |
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| 17 | include the IDT copyright notice, this paragraph, and the preceeding |
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| 18 | two paragraphs in the transferred software. |
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| 19 | |
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| 20 | COPYRIGHT IDT CORPORATION 1996 |
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| 21 | LICENSED MATERIAL - PROGRAM PROPERTY OF IDT |
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| 22 | |
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| 23 | */ |
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| 24 | |
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| 25 | /* |
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| 26 | * $Id$ |
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| 27 | */ |
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| 28 | |
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| 29 | #include <rtems/mips/iregdef.h> |
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| 30 | #include <rtems/mips/idtcpu.h> |
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| 31 | #include <rtems/asm.h> |
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| 32 | |
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| 33 | |
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| 34 | .text |
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| 35 | |
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| 36 | #if __mips == 1 |
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| 37 | /* |
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| 38 | ** ret_tlblo -- returns the 'entrylo' contents for the TLB |
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| 39 | ** 'c' callable - as ret_tlblo(index) - where index is the |
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| 40 | ** tlb entry to return the lo value for - if called from assembly |
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| 41 | ** language then index should be in register a0. |
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| 42 | */ |
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| 43 | FRAME(ret_tlblo,sp,0,ra) |
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| 44 | .set noreorder |
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| 45 | mfc0 t0,C0_SR # save sr |
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| 46 | nop |
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| 47 | and t0,~SR_PE # dont inadvertantly clear PE |
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| 48 | mtc0 zero,C0_SR # clear interrupts |
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| 49 | mfc0 t1,C0_TLBHI # save pid |
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| 50 | sll a0,TLBINX_INXSHIFT # position index |
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| 51 | mtc0 a0,C0_INX # write to index register |
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| 52 | nop |
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| 53 | tlbr # put tlb entry in entrylo and hi |
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| 54 | nop |
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| 55 | mfc0 v0,C0_TLBLO # get the requested entry lo |
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| 56 | mtc0 t1,C0_TLBHI # restore pid |
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| 57 | mtc0 t0,C0_SR # restore status register |
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| 58 | j ra |
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| 59 | nop |
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| 60 | .set reorder |
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| 61 | ENDFRAME(ret_tlblo) |
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| 62 | #endif |
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| 63 | #if __mips == 3 |
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| 64 | /* |
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| 65 | ** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB |
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| 66 | ** 'c' callable - as ret_tlblo(index) - where index is the |
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| 67 | ** tlb entry to return the lo value for - if called from assembly |
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| 68 | ** language then index should be in register a0. |
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| 69 | */ |
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| 70 | FRAME(ret_tlblo0,sp,0,ra) |
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| 71 | mfc0 t0,C0_SR # save sr |
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| 72 | mtc0 zero,C0_SR # clear interrupts |
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| 73 | mfc0 t1,C0_TLBHI # save pid |
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| 74 | mtc0 a0,C0_INX # write to index register |
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| 75 | .set noreorder |
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| 76 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 77 | .set reorder |
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| 78 | tlbr # put tlb entry in entrylo and hi |
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| 79 | .set noreorder |
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| 80 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 81 | .set reorder |
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| 82 | mfc0 v0,C0_TLBLO0 # get the requested entry lo |
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| 83 | mtc0 t1,C0_TLBHI # restore pid |
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| 84 | mtc0 t0,C0_SR # restore status register |
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| 85 | j ra |
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| 86 | ENDFRAME(ret_tlblo0) |
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| 87 | |
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| 88 | FRAME(ret_tlblo1,sp,0,ra) |
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| 89 | mfc0 t0,C0_SR # save sr |
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| 90 | mtc0 zero,C0_SR # clear interrupts |
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| 91 | mfc0 t1,C0_TLBHI # save pid |
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| 92 | mtc0 a0,C0_INX # write to index register |
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| 93 | .set noreorder |
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| 94 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 95 | .set reorder |
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| 96 | tlbr # put tlb entry in entrylo and hi |
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| 97 | .set noreorder |
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| 98 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 99 | .set reorder |
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| 100 | mfc0 v0,C0_TLBLO1 # get the requested entry lo |
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| 101 | mtc0 t1,C0_TLBHI # restore pid |
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| 102 | mtc0 t0,C0_SR # restore status register |
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| 103 | j ra |
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| 104 | ENDFRAME(ret_tlblo1) |
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| 105 | |
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| 106 | /* |
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| 107 | ** ret_pagemask(index) -- return pagemask contents of tlb entry "index" |
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| 108 | */ |
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| 109 | FRAME(ret_pagemask,sp,0,ra) |
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| 110 | mfc0 t0,C0_SR # save sr |
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| 111 | mtc0 zero,C0_SR # disable interrupts |
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| 112 | mfc0 t1,C0_TLBHI # save current pid |
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| 113 | mtc0 a0,C0_INX # drop it in C0 register |
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| 114 | .set noreorder |
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| 115 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 116 | .set reorder |
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| 117 | tlbr # read entry to entry hi/lo |
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| 118 | .set noreorder |
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| 119 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 120 | .set reorder |
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| 121 | mfc0 v0,C0_PAGEMASK # to return value |
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| 122 | mtc0 t1,C0_TLBHI # restore current pid |
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| 123 | mtc0 t0,C0_SR # restore sr |
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| 124 | j ra |
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| 125 | ENDFRAME(ret_pagemask) |
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| 126 | |
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| 127 | /* |
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| 128 | ** ret_tlbwired(void) -- return wired register |
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| 129 | */ |
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| 130 | FRAME(ret_tlbwired,sp,0,ra) |
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| 131 | mfc0 v0,C0_WIRED |
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| 132 | j ra |
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| 133 | ENDFRAME(ret_tlbwired) |
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| 134 | #endif |
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| 135 | |
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| 136 | /* |
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| 137 | ** ret_tlbhi -- return the tlb entry high content for tlb entry |
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| 138 | ** index |
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| 139 | */ |
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| 140 | FRAME(ret_tlbhi,sp,0,ra) |
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| 141 | #if __mips == 1 |
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| 142 | .set noreorder |
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| 143 | mfc0 t0,C0_SR # save sr |
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| 144 | nop |
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| 145 | and t0,~SR_PE |
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| 146 | mtc0 zero,C0_SR # disable interrupts |
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| 147 | mfc0 t1,C0_TLBHI # save current pid |
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| 148 | sll a0,TLBINX_INXSHIFT # position index |
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| 149 | mtc0 a0,C0_INX # drop it in C0 register |
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| 150 | nop |
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| 151 | tlbr # read entry to entry hi/lo |
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| 152 | nop |
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| 153 | mfc0 v0,C0_TLBHI # to return value |
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| 154 | mtc0 t1,C0_TLBHI # restore current pid |
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| 155 | mtc0 t0,C0_SR # restore sr |
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| 156 | j ra |
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| 157 | nop |
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| 158 | .set reorder |
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| 159 | #endif |
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| 160 | #if __mips == 3 |
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| 161 | mfc0 t0,C0_SR # save sr |
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| 162 | mtc0 zero,C0_SR # disable interrupts |
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| 163 | mfc0 t1,C0_TLBHI # save current pid |
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| 164 | mtc0 a0,C0_INX # drop it in C0 register |
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| 165 | .set noreorder |
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| 166 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 167 | .set reorder |
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| 168 | tlbr # read entry to entry hi/lo0/lo1/mask |
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| 169 | .set noreorder |
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| 170 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 171 | .set reorder |
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| 172 | mfc0 v0,C0_TLBHI # to return value |
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| 173 | mtc0 t1,C0_TLBHI # restore current pid |
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| 174 | mtc0 t0,C0_SR # restore sr |
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| 175 | j ra |
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| 176 | #endif |
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| 177 | ENDFRAME(ret_tlbhi) |
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| 178 | |
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| 179 | /* |
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| 180 | ** ret_tlbpid() -- return tlb pid contained in the current entry hi |
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| 181 | */ |
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| 182 | FRAME(ret_tlbpid,sp,0,ra) |
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| 183 | #if __mips == 1 |
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| 184 | .set noreorder |
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| 185 | mfc0 v0,C0_TLBHI # fetch tlb high |
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| 186 | nop |
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| 187 | and v0,TLBHI_PIDMASK # isolate and position |
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| 188 | srl v0,TLBHI_PIDSHIFT |
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| 189 | j ra |
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| 190 | nop |
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| 191 | .set reorder |
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| 192 | #endif |
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| 193 | #if __mips == 3 |
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| 194 | mfc0 v0,C0_TLBHI # to return value |
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| 195 | nop |
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| 196 | and v0,TLBHI_PIDMASK |
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| 197 | j ra |
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| 198 | #endif |
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| 199 | ENDFRAME(ret_tlbpid) |
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| 200 | |
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| 201 | /* |
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| 202 | ** tlbprobe(address, pid) -- probe the tlb to see if address is currently |
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| 203 | ** mapped |
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| 204 | ** a0 = vpn - virtual page numbers are 0=0 1=0x1000, 2=0x2000... |
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| 205 | ** virtual page numbers for the r3000 are in |
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| 206 | ** entry hi bits 31-12 |
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| 207 | ** a1 = pid - this is a process id ranging from 0 to 63 |
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| 208 | ** this process id is shifted left 6 bits and or'ed into |
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| 209 | ** the entry hi register |
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| 210 | ** returns an index value (0-63) if successful -1 -f not |
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| 211 | */ |
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| 212 | FRAME(tlbprobe,sp,0,ra) |
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| 213 | #if __mips == 1 |
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| 214 | .set noreorder |
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| 215 | mfc0 t0,C0_SR /* fetch status reg */ |
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| 216 | and a0,TLBHI_VPNMASK /* isolate just the vpn */ |
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| 217 | and t0,~SR_PE /* don't inadvertantly clear pe */ |
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| 218 | mtc0 zero,C0_SR |
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| 219 | mfc0 t1,C0_TLBHI |
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| 220 | sll a1,TLBHI_PIDSHIFT /* possition the pid */ |
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| 221 | and a1,TLBHI_PIDMASK |
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| 222 | or a0,a1 /* build entry hi value */ |
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| 223 | mtc0 a0,C0_TLBHI |
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| 224 | nop |
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| 225 | tlbp /* do the probe */ |
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| 226 | nop |
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| 227 | mfc0 v1,C0_INX |
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| 228 | li v0,-1 |
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| 229 | bltz v1,1f |
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| 230 | nop |
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| 231 | sra v0,v1,TLBINX_INXSHIFT /* get index positioned for return */ |
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| 232 | 1: |
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| 233 | mtc0 t1,C0_TLBHI /* restore tlb hi */ |
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| 234 | mtc0 t0,C0_SR /* restore the status reg */ |
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| 235 | j ra |
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| 236 | nop |
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| 237 | .set reorder |
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| 238 | #endif |
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| 239 | #if __mips == 3 |
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| 240 | mfc0 t0,C0_SR # save sr |
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| 241 | mtc0 zero,C0_SR # disable interrupts |
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| 242 | mfc0 t1,C0_TLBHI # save current pid |
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| 243 | and a0,TLBHI_VPN2MASK # construct tlbhi for probe |
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| 244 | and a1,TLBHI_PIDMASK |
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| 245 | or a0,a1 |
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| 246 | mtc0 a0,C0_TLBHI |
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| 247 | .set noreorder |
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| 248 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 249 | .set reorder |
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| 250 | tlbp # probe entry to entry hi/lo0/lo1/mask |
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| 251 | .set noreorder |
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| 252 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 253 | .set reorder |
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| 254 | mfc0 v1,C0_INX |
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| 255 | li v0,-1 |
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| 256 | bltz v1,1f |
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| 257 | move v0,v1 |
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| 258 | 1: mtc0 t1,C0_TLBHI # restore current pid |
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| 259 | mtc0 t0,C0_SR # restore sr |
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| 260 | j ra |
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| 261 | #endif |
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| 262 | ENDFRAME(tlbprobe) |
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| 263 | |
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| 264 | /* |
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| 265 | ** resettlb(index) Invalidate the TLB entry specified by index |
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| 266 | */ |
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| 267 | FRAME(resettlb,sp,0,ra) |
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| 268 | #if __mips == 1 |
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| 269 | .set noreorder |
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| 270 | mfc0 t0,C0_TLBHI # fetch the current hi |
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| 271 | mfc0 v0,C0_SR # fetch the status reg. |
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| 272 | li t2,K0BASE&TLBHI_VPNMASK |
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| 273 | and v0,~SR_PE # dont inadvertantly clear PE |
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| 274 | mtc0 zero,C0_SR |
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| 275 | mtc0 t2,C0_TLBHI # set up tlbhi |
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| 276 | mtc0 zero,C0_TLBLO |
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| 277 | sll a0,TLBINX_INXSHIFT |
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| 278 | mtc0 a0,C0_INX |
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| 279 | nop |
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| 280 | tlbwi # do actual invalidate |
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| 281 | nop |
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| 282 | mtc0 t0,C0_TLBHI |
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| 283 | mtc0 v0,C0_SR |
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| 284 | j ra |
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| 285 | nop |
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| 286 | .set reorder |
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| 287 | #endif |
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| 288 | #if __mips == 3 |
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| 289 | li t2,K0BASE&TLBHI_VPN2MASK |
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| 290 | mfc0 t0,C0_TLBHI # save current TLBHI |
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| 291 | mfc0 v0,C0_SR # save SR and disable interrupts |
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| 292 | mtc0 zero,C0_SR |
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| 293 | mtc0 t2,C0_TLBHI # invalidate entry |
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| 294 | mtc0 zero,C0_TLBLO0 |
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| 295 | mtc0 zero,C0_TLBLO1 |
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| 296 | mtc0 a0,C0_INX |
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| 297 | .set noreorder |
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| 298 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 299 | .set reorder |
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| 300 | tlbwi |
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| 301 | .set noreorder |
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| 302 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 303 | .set reorder |
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| 304 | mtc0 t0,C0_TLBHI |
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| 305 | mtc0 v0,C0_SR |
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| 306 | j ra |
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| 307 | #endif |
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| 308 | ENDFRAME(resettlb) |
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| 309 | |
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| 310 | #if __mips == 1 |
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| 311 | /* |
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| 312 | ** Setup TLB entry |
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| 313 | ** |
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| 314 | ** map_tlb(index, tlbhi, phypage) |
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| 315 | ** a0 = TLB entry index |
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| 316 | ** a1 = virtual page number and PID |
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| 317 | ** a2 = physical page |
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| 318 | */ |
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| 319 | FRAME(map_tlb,sp,0,ra) |
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| 320 | .set noreorder |
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| 321 | sll a0,TLBINX_INXSHIFT |
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| 322 | mfc0 v0,C0_SR # fetch the current status |
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| 323 | mfc0 a3,C0_TLBHI # save the current hi |
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| 324 | and v0,~SR_PE # dont inadvertantly clear parity |
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| 325 | |
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| 326 | mtc0 zero,C0_SR |
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| 327 | mtc0 a1,C0_TLBHI # set the hi entry |
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| 328 | mtc0 a2,C0_TLBLO # set the lo entry |
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| 329 | mtc0 a0,C0_INX # load the index |
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| 330 | nop |
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| 331 | tlbwi # put the hi/lo in tlb entry indexed |
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| 332 | nop |
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| 333 | mtc0 a3,C0_TLBHI # put back the tlb hi reg |
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| 334 | mtc0 v0,C0_SR # restore the status register |
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| 335 | j ra |
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| 336 | nop |
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| 337 | .set reorder |
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| 338 | ENDFRAME(map_tlb) |
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| 339 | #endif |
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| 340 | #if __mips == 3 |
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| 341 | /* |
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| 342 | ** Setup R4000 TLB entry |
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| 343 | ** |
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| 344 | ** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd) |
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| 345 | ** a0 = TLB entry index and page mask |
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| 346 | ** a1 = virtual page number and PID |
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| 347 | ** a2 = pte -- contents of even pte |
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| 348 | ** a3 = pte -- contents of odd pte |
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| 349 | */ |
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| 350 | FRAME(map_tlb4000,sp,0,ra) |
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| 351 | and t2,a0,TLBPGMASK_MASK |
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| 352 | and a0,TLBINX_INXMASK |
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| 353 | mfc0 t1,C0_TLBHI # save current TLBPID |
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| 354 | mfc0 v0,C0_SR # save SR and disable interrupts |
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| 355 | mtc0 zero,C0_SR |
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| 356 | mtc0 t2,C0_PAGEMASK # set |
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| 357 | mtc0 a1,C0_TLBHI # set VPN and TLBPID |
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| 358 | mtc0 a2,C0_TLBLO0 # set PPN and access bits |
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| 359 | mtc0 a3,C0_TLBLO1 # set PPN and access bits |
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| 360 | mtc0 a0,C0_INX # set INDEX to wired entry |
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| 361 | .set noreorder |
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| 362 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 363 | .set reorder |
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| 364 | tlbwi # drop it in |
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| 365 | .set noreorder |
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| 366 | nop; nop; nop; nop; nop; nop; nop; nop |
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| 367 | .set reorder |
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| 368 | mtc0 t1,C0_TLBHI # restore TLBPID |
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| 369 | mtc0 v0,C0_SR # restore SR |
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| 370 | j ra |
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| 371 | ENDFRAME(map_tlb4000) |
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| 372 | #endif |
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| 373 | |
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| 374 | |
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| 375 | /* |
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| 376 | ** Set current TLBPID. This assumes PID is positioned correctly in reg. |
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| 377 | ** a0. |
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| 378 | */ |
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| 379 | FRAME(set_tlbpid,sp,0,ra) |
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| 380 | .set noreorder |
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| 381 | mtc0 a0,C0_TLBHI |
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| 382 | j ra |
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| 383 | nop |
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| 384 | .set reorder |
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| 385 | ENDFRAME(set_tlbpid) |
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| 386 | |
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