4.104.114.84.95
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1 | /* USC constants */ |
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2 | |
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3 | #ifndef _USC_H__ |
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4 | #define _USC_H__ |
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5 | |
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6 | |
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7 | #define USC_REG_BASE (0x1D000000 | 0xA0000000) |
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8 | |
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9 | /* Internal register addresses */ |
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10 | #define SYSTEM (USC_REG_BASE + 0x73) |
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11 | |
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12 | #define INT_CFG0 (USC_REG_BASE + 0xE0) |
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13 | #define INT_CFG1 (USC_REG_BASE + 0xE4) |
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14 | #define INT_CFG2 (USC_REG_BASE + 0xE8) |
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15 | #define INT_STAT (USC_REG_BASE + 0xEC) |
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16 | |
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17 | #define WD_HBI (USC_REG_BASE + 0xF4) |
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18 | |
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19 | #define INT_CFG3 (USC_REG_BASE + 0x158) |
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20 | |
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21 | /* INT_CFGx register masks */ |
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22 | #define HBI_MASK 0x00200000 /* Heartbeat timer interrupt mask */ |
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23 | #define WDI_MASK 0x00400000 /* Watchdog timer interrupt mask */ |
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24 | #define MODE_TOTEM_POLE 0x20000000 /* Totem Pole Output Mode */ |
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25 | |
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26 | /* WD_HBI register bits */ |
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27 | #define WD_EN 0x00800000 /* Watchdog enable */ |
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28 | #define HBI_4000_PS 0x00200000 /* Heartbeat timer prescaler = 4000 */ |
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29 | #define WD_INIT 0x10 /* Watchdog reset pattern (written to byte 2 in WD_HBI register) */ |
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30 | |
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31 | |
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32 | #endif /* _USC_H__ */ |
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