1 | /** |
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2 | * @file |
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3 | * |
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4 | * This routine starts the application. It includes application, |
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5 | * board, and monitor specific initialization and configuration. |
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6 | * The generic CPU dependent initialization has been performed |
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7 | * before this routine is invoked. |
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8 | * |
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9 | * Modification History: |
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10 | * 12/10/01 A.Ferrer, NASA/GSFC, Code 582 |
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11 | * Set interrupt mask to 0xAF00 (Line 139). |
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12 | */ |
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13 | |
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14 | /* |
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15 | * COPYRIGHT (c) 1989-2012. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <string.h> |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <bsp/mongoose-v.h> |
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27 | #include <libcpu/isr_entries.h> |
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28 | #include <bsp/irq-generic.h> |
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29 | |
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30 | void bsp_start( void ); |
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31 | void clear_cache( void ); |
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32 | extern void _sys_exit(int); |
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33 | extern void mips_gdb_stub_install(void); |
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34 | |
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35 | /* |
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36 | * bsp_start |
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37 | * |
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38 | * This routine does the bulk of the system initialization. |
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39 | */ |
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40 | void bsp_start( void ) |
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41 | { |
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42 | /* mask off any interrupts */ |
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43 | MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 ); |
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44 | |
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45 | /* reset the config register & clear any pending peripheral interrupts */ |
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46 | MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 ); |
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47 | MONGOOSEV_WRITE( |
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48 | MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, MONGOOSEV_UART_CMD_RESET_BOTH_PORTS ); |
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49 | MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 ); |
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50 | |
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51 | /* reset both timers */ |
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52 | MONGOOSEV_WRITE_REGISTER( |
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53 | MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff); |
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54 | MONGOOSEV_WRITE_REGISTER( |
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55 | MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0); |
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56 | |
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57 | MONGOOSEV_WRITE_REGISTER( |
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58 | MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff); |
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59 | MONGOOSEV_WRITE_REGISTER( |
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60 | MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0); |
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61 | |
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62 | /* clear any pending interrupts */ |
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63 | MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, 0xffffffff ); |
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64 | |
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65 | /* clear any writable bits in the cause register */ |
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66 | mips_set_cause( 0 ); |
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67 | |
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68 | /* set interrupt mask, but globally off. */ |
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69 | |
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70 | /* |
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71 | * Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 | |
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72 | * periph | unused | FPU | unused | timer2 | timer1 | swint1 | swint2 | |
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73 | * extern | | | | | | | | |
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74 | * |
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75 | * 1 0 1 0 0 1 0 0 |
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76 | * |
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77 | * 0x8C00 Enable only internal Mongoose V timers. |
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78 | * 0xA400 Enable Peripherial ints, FPU and timer1 |
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79 | * 0x0400 Timer1 only |
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80 | */ |
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81 | |
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82 | /* mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) ); */ |
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83 | |
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84 | /* to start up, only enable coprocessor 0 & timer int. per-task |
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85 | * processor settings will be applied as they are created, this |
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86 | * is just to configure the processor for startup |
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87 | */ |
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88 | mips_set_sr( (SR_CU0 | 0x400) ); |
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89 | |
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90 | bsp_interrupt_initialize(); |
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91 | } |
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92 | |
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93 | void clear_cache( void ) |
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94 | { |
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95 | promCopyIcacheFlush(); |
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96 | promCopyDcacheFlush(); |
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97 | } |
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