source: rtems/c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c @ 8536b67

4.115
Last change on this file since 8536b67 was 8536b67, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 8, 2014 at 8:06:52 PM

Move Mongoose-V specific devices into BSP.

Putting the duart in libcpu was very optimistic and presumptuous.
It has never been used again on another SoC and is BSP specific.

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/**
2 *  @file
3 * 
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Modification History:
10 *        12/10/01  A.Ferrer, NASA/GSFC, Code 582
11 *           Set interrupt mask to 0xAF00 (Line 139).
12 */
13
14/*
15 *  COPYRIGHT (c) 1989-2012.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.org/license/LICENSE.
21 */
22 
23#include <string.h>
24
25#include <bsp.h>
26#include <bsp/mongoose-v.h>
27#include <libcpu/isr_entries.h>
28#include <bsp/irq-generic.h>
29
30void bsp_start( void );
31void clear_cache( void );
32extern void _sys_exit(int);
33extern void mips_gdb_stub_install(void);
34
35/*
36 *  bsp_start
37 *
38 *  This routine does the bulk of the system initialization.
39 */
40void bsp_start( void )
41{
42 /* mask off any interrupts */
43 MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
44
45 /* reset the config register & clear any pending peripheral interrupts */
46 MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
47 MONGOOSEV_WRITE(
48   MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, MONGOOSEV_UART_CMD_RESET_BOTH_PORTS );
49 MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
50
51 /* reset both timers */
52 MONGOOSEV_WRITE_REGISTER(
53   MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff);
54 MONGOOSEV_WRITE_REGISTER(
55   MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
56
57 MONGOOSEV_WRITE_REGISTER(
58   MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff);
59 MONGOOSEV_WRITE_REGISTER(
60   MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
61
62 /* clear any pending interrupts */
63 MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, 0xffffffff );
64
65 /* clear any writable bits in the cause register */
66 mips_set_cause( 0 );
67
68 /* set interrupt mask, but globally off. */
69
70 /*
71  *  Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit  9 | Bit  8 |
72  *  periph | unused |  FPU   | unused | timer2 | timer1 | swint1 | swint2 |
73  *  extern |        |        |        |        |        |        |        |
74  *
75  *    1        0        1        0        0        1        0        0
76  *
77  *    0x8C00   Enable only internal Mongoose V timers.
78  *    0xA400   Enable Peripherial ints, FPU and timer1
79  *    0x0400   Timer1 only
80  */
81
82  /* mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) ); */
83
84  /* to start up, only enable coprocessor 0 & timer int. per-task
85   * processor settings will be applied as they are created, this
86   * is just to configure the processor for startup
87   */
88  mips_set_sr( (SR_CU0 | 0x400) );
89
90  bsp_interrupt_initialize();
91}
92
93void clear_cache( void )
94{
95   promCopyIcacheFlush();
96   promCopyDcacheFlush();
97}
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