1 | /* |
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2 | ** |
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3 | ** Section 1: Registers |
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4 | ** |
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5 | */ |
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6 | |
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7 | /* |
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8 | ** |
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9 | */ |
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10 | #define PMON_ADDRESS 0xbfc00000 |
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11 | |
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12 | |
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13 | |
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14 | /* |
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15 | ** Mongoose V Peripheral Function Registers |
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16 | */ |
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17 | |
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18 | #define MG5_COMMAND_REG 0xfffe0180 |
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19 | |
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20 | /* |
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21 | ** Extended Interrupt Registers |
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22 | ** These registers are used as follows: |
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23 | ** 1. The mask register is used to allow peripheral function and external |
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24 | ** interrupts to function. To enable an interrupt, set the appropriate |
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25 | ** bit. |
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26 | ** 2. The status register contains the state of the peripheral functions |
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27 | ** and external devices. This register should be read to poll devices |
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28 | ** such as the uart when the interrupts are not enabled. Writing to this |
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29 | ** register will clear the interrupt. |
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30 | ** 3. The Cause register is similar to the status register, with the |
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31 | ** exception that it only shows the bits that are set in the mask |
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32 | ** register. This register should be read to determine which interrupt(s) |
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33 | ** need to be serviced. This register when written to will CAUSE the interrupt. |
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34 | */ |
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35 | #define MG5_INT_STATUS_REG 0xfffe0184 /* Read to determine state/Write to clear */ |
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36 | #define MG5_INT_CAUSE_REG 0xfffe0188 /* Read to determine int/Write to cause int */ |
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37 | #define MG5_INT_MASK_REG 0xfffe018c /* Set bit here to enable int */ |
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38 | |
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39 | /* |
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40 | ** EDAC Registers |
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41 | */ |
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42 | #define MG5_EDAC_ADDR_REG 0xfffe0190 /* edac error address */ |
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43 | #define MG5_EDAC_PARITY_REG 0xfffe0194 /* edac parity */ |
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44 | |
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45 | /* |
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46 | ** High speed serial port registers |
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47 | ** This section is reserved for future Mongoose Processors |
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48 | */ |
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49 | |
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50 | /* |
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51 | ** Floating Point Register |
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52 | */ |
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53 | #define MG5_FPU_CNTRL_REG 0xfffe0020 /* FPU control register */ |
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54 | |
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55 | /* |
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56 | ** MAVN Registers |
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57 | */ |
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58 | #define MG5_MAVN_TEST_REG 0xfffe01b4 /* test mavn */ |
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59 | #define MG5_MAVN_PRIVLEGE_REG 0xfffe01b8 /* privlege bits */ |
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60 | #define MG5_MAVN_VIOLATION_REG 0xfffe01bc /* address of violation */ |
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61 | #define MG5_MAVN_RANGE_0_REG 0xfffe01c0 /* Range 0 */ |
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62 | #define MG5_MAVN_RANGE_1_REG 0xfffe01c4 /* Range 1 */ |
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63 | #define MG5_MAVN_RANGE_2_REG 0xfffe01c8 /* Range 2 */ |
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64 | #define MG5_MAVN_RANGE_3_REG 0xfffe01cc /* Range 3 */ |
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65 | #define MG5_MAVN_RANGE_4_REG 0xfffe01d0 /* Range 4 */ |
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66 | #define MG5_MAVN_RANGE_5_REG 0xfffe01d4 /* Range 5 */ |
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67 | |
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68 | |
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69 | /* |
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70 | ** Uart Specific Peripheral Function Registers |
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71 | */ |
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72 | #define MG5_UART_0_RX_REG 0xfffe01e8 |
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73 | #define MG5_UART_0_TX_REG 0xfffe01ec |
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74 | #define MG5_UART_0_BAUD_REG 0xfffe01f0 |
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75 | #define MG5_UART_1_RX_REG 0xfffe01f4 |
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76 | #define MG5_UART_1_TX_REG 0xfffe01f8 |
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77 | #define MG5_UART_1_BAUD_REG 0xfffe01fc |
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78 | |
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79 | |
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80 | /* |
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81 | ** Section 2: Bit definitions |
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82 | ** |
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83 | */ |
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84 | |
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85 | /* |
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86 | ** Command Register Bits - defined from 31 to 0 |
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87 | */ |
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88 | #define EDAC_ENABLE_BIT 0x80000000 |
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89 | #define EDAC_OVERRIDE_BIT 0x40000000 |
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90 | /* 29 - 16 reserved */ |
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91 | #define UART_1_PARITY_EVEN_BIT 0x00008000 |
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92 | #define UART_1_PARITY_ENABLE_BIT 0x00004000 |
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93 | #define UART_1_RTS_BIT 0x00002000 |
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94 | #define UART_1_TX_ENABLE_BIT 0x00001000 |
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95 | #define UART_1_RX_ENABLE_BIT 0x00000800 |
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96 | #define UART_1_TX_BREAK_BIT 0x00000400 |
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97 | |
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98 | #define UART_0_PARITY_EVEN_BIT 0x00000200 |
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99 | #define UART_0_PARITY_ENABLE_BIT 0x00000100 |
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100 | #define UART_0_RTS_BIT 0x00000080 |
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101 | #define UART_0_TX_ENABLE_BIT 0x00000040 |
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102 | #define UART_0_RX_ENABLE_BIT 0x00000020 |
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103 | #define UART_0_TX_BREAK_BIT 0x00000010 |
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104 | |
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105 | #define UART_LOOPBACK_MODE_BIT 0x00000008 |
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106 | #define UART_CTSN_TEST_BIT 0x00000004 |
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107 | #define UART_RESET_BIT 0x00000002 |
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108 | |
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109 | |
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110 | /* |
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111 | ** Interrupt Status/Cause/Mask register bits - from 31 to 0 |
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112 | */ |
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113 | #define EDAC_SERR_BIT 0x80000000 |
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114 | #define EDAC_MERR_BIT 0x40000000 |
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115 | /* 29 - 24 reserved */ |
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116 | #define UART_0_RX_READY_BIT 0x00008000 |
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117 | #define UART_0_TX_READY_BIT 0x00004000 |
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118 | #define UART_0_TX_EMPTY_BIT 0x00002000 |
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119 | #define UART_0_RX_OVERRUN_BIT 0x00001000 |
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120 | #define UART_0_FRAME_ERR_BIT 0x00000800 |
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121 | #define UART_0_RESERVED_BIT 0x00000400 |
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122 | #define UART_1_RX_READY_BIT 0x00200000 |
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123 | #define UART_1_TX_READY_BIT 0x00100000 |
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124 | #define UART_1_TX_EMPTY_BIT 0x00080000 |
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125 | #define UART_1_RX_OVERRUN_BIT 0x00040000 |
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126 | #define UART_1_FRAME_ERR_BIT 0x00020000 |
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127 | #define UART_1_RESERVED_BIT 0x00010000 |
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128 | #define MAVN_WRITE_ACC_BIT 0x00400000 |
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129 | #define MAVN_READ_ACC_BIT 0x00800000 |
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130 | #define EXTERN_INT_9_BIT 0x00000200 |
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131 | #define EXTERN_INT_8_BIT 0x00000100 |
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132 | #define EXTERN_INT_7_BIT 0x00000080 |
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133 | #define EXTERN_INT_6_BIT 0x00000040 |
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134 | #define EXTERN_INT_5_BIT 0x00000020 |
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135 | #define EXTERN_INT_4_BIT 0x00000010 |
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136 | #define EXTERN_INT_3_BIT 0x00000008 |
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137 | #define EXTERN_INT_2_BIT 0x00000004 |
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138 | #define EXTERN_INT_1_BIT 0x00000002 |
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139 | #define EXTERN_INT_0_BIT 0x00000001 |
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140 | |
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141 | |
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142 | /* |
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143 | ** MAVN Range Bits |
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144 | */ |
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145 | |
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146 | #define MAVN_RANGE_0_WRITE_BIT 0x00000001 |
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147 | #define MAVN_RANGE_1_WRITE_BIT 0x00000002 |
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148 | #define MAVN_RANGE_2_WRITE_BIT 0x00000004 |
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149 | #define MAVN_RANGE_3_WRITE_BIT 0x00000008 |
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150 | #define MAVN_RANGE_4_WRITE_BIT 0x00000010 |
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151 | #define MAVN_RANGE_5_WRITE_BIT 0x00000020 |
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152 | |
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153 | #define MAVN_GLOBAL_WRITE_BIT 0x00000200 |
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154 | |
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155 | |
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156 | #define MAVN_RANGE_0_READ_BIT 0x00000400 |
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157 | #define MAVN_RANGE_1_READ_BIT 0x00000800 |
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158 | #define MAVN_RANGE_2_READ_BIT 0x00001000 |
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159 | #define MAVN_RANGE_3_READ_BIT 0x00002000 |
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160 | #define MAVN_RANGE_4_READ_BIT 0x00004000 |
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161 | #define MAVN_RANGE_5_READ_BIT 0x00008000 |
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162 | |
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163 | #define MAVN_GLOBAL_READ_BIT 0x00080000 |
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164 | |
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165 | #define MAVN_ENABLE_BIT 0x80000000 |
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166 | #define MAVN_TEST_BIT 0x40000000 |
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167 | |
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168 | #define MAVN_RANGE_NO_ACESS 0x00000000 |
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169 | |
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170 | #define MAVN_PS_CODE_512 0x00000009 |
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171 | #define MAVN_PS_CODE_1K 0x0000000a |
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172 | #define MAVN_PS_CODE_2K 0x0000000b |
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173 | #define MAVN_PS_CODE_4K 0x0000000c |
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174 | #define MAVN_PS_CODE_8K 0x0000000d |
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175 | #define MAVN_PS_CODE_16K 0x0000000e |
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176 | #define MAVN_PS_CODE_32K 0x0000000f |
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177 | #define MAVN_PS_CODE_64K 0x00000010 |
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178 | #define MAVN_PS_CODE_128K 0x00000011 |
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179 | #define MAVN_PS_CODE_256K 0x00000012 |
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180 | #define MAVN_PS_CODE_512K 0x00000013 |
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181 | #define MAVN_PS_CODE_1M 0x00000014 |
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182 | #define MAVN_PS_CODE_2M 0x00000015 |
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183 | |
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184 | /* |
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185 | ** FPU Control Bits |
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186 | */ |
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187 | #define FPU_CNTRL_CONDITION 0x00800000 |
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188 | #define FPU_CNTRL_EXCEPT_E 0x00020000 |
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189 | #define FPU_CNTRL_EXCEPT_V 0x00010000 |
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190 | #define FPU_CNTRL_EXCEPT_Z 0x00008000 |
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191 | #define FPU_CNTRL_EXCEPT_O 0x00004000 |
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192 | #define FPU_CNTRL_EXCEPT_U 0x00002000 |
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193 | #define FPU_CNTRL_EXCEPT_I 0x00001000 |
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194 | #define FPU_CNTRL_TRAP_V 0x00000800 |
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195 | #define FPU_CNTRL_TRAP_Z 0x00000400 |
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196 | #define FPU_CNTRL_TRAP_O 0x00000200 |
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197 | #define FPU_CNTRL_TRAP_U 0x00000100 |
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198 | #define FPU_CNTRL_TRAP_I 0x00000080 |
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199 | #define FPU_CNTRL_STICKY_V 0x00000040 |
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200 | #define FPU_CNTRL_STICKY_Z 0x00000020 |
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201 | #define FPU_CNTRL_STICKY_O 0x00000010 |
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202 | #define FPU_CNTRL_STICKY_U 0x00000008 |
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203 | #define FPU_CNTRL_STICKY_I 0x00000004 |
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204 | #define FPU_CNTRL_ROUND_RN 0x00000000 |
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205 | #define FPU_CNTRL_ROUND_RZ 0x00000001 |
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206 | #define FPU_CNTRL_ROUND_RP 0x00000002 |
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207 | #define FPU_CNTRL_ROUND_RM 0x00000003 |
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208 | |
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209 | #define FPU_EXCEPTIONS FPU_CNTRL_TRAP_V|FPU_CNTRL_TRAP_Z|FPU_CNTRL_TRAP_O|FPU_CNTRL_TRAP_U|FPU_CNTRL_TRAP_I |
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210 | #define FPU_CONFIGURATION FPU_EXCEPTIONS|FPU_CNTRL_ROUND_RN |
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211 | |
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212 | /* |
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213 | ** |
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214 | ** Section 3 -- Masks |
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215 | ** |
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216 | */ |
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217 | |
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218 | #define UART_TX_BAUD_MASK 0x00007FFF |
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219 | #define UART_RX_BAUD_MASK 0x7FFF0000 |
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220 | #define UART_DATA_MASK 0x000000FF |
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221 | |
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222 | #define UART_TX_BAUD_4800(x) ((((x*1000000)/4800) - 1) & UART_TX_BAUD_MASK) |
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223 | #define UART_TX_BAUD_9600(x) ((((x*1000000)/9600) - 1) & UART_TX_BAUD_MASK) |
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224 | #define UART_TX_BAUD_19200(x) ((((x*1000000)/19200) - 1)& UART_TX_BAUD_MASK) |
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225 | #define UART_TX_BAUD_38400(x) ((((x*1000000)/38400) - 1)& UART_TX_BAUD_MASK) |
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226 | |
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227 | #define UART_RX_BAUD_4800(x) (((((x*1000000)/4800) - 1) << 16) & UART_RX_BAUD_MASK) |
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228 | #define UART_RX_BAUD_9600(x) (((((x*1000000)/9600) - 1) << 16) & UART_RX_BAUD_MASK) |
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229 | #define UART_RX_BAUD_19200(x) (((((x*1000000)/19200) - 1) << 16)& UART_RX_BAUD_MASK) |
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230 | #define UART_RX_BAUD_38400(x) (((((x*1000000)/38400) - 1) << 16)& UART_RX_BAUD_MASK) |
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231 | |
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232 | #define UART_BAUD_4800(x) ((((x*1000000)/4800) - 1) & UART_TX_BAUD_MASK) | (((((x*1000000)/4800) - 1) << 16) & UART_RX_BAUD_MASK) |
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233 | #define UART_BAUD_9600(x) ((((x*1000000)/9600) - 1) & UART_TX_BAUD_MASK) | (((((x*1000000)/9600) - 1) << 16) & UART_RX_BAUD_MASK) |
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234 | #define UART_BAUD_19200(x) ((((x*1000000)/19200) - 1)& UART_TX_BAUD_MASK) | (((((x*1000000)/19200) - 1) << 16)& UART_RX_BAUD_MASK) |
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235 | #define UART_BAUD_38400(x) ((((x*1000000)/38400) - 1)& UART_TX_BAUD_MASK) | (((((x*1000000)/38400) - 1) << 16)& UART_RX_BAUD_MASK) |
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236 | |
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237 | #define EDAC_PARITY_MASK 0x000000FF |
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238 | |
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239 | #define MAVN_START_ADDR_MASK 0xFFFFFE00 |
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240 | #define MAVN_PS_CODE_MASK 0x0000001F |
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241 | |
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242 | |
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243 | |
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244 | |
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245 | |
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246 | |
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247 | /* lr33000.h - defines for LSI Logic LR33000 */ |
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248 | |
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249 | /* Define counter/timer register addresses */ |
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250 | #define M_TIC1 0xfffe0000 /* timer 1 initial count */ |
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251 | #define M_TC1 0xfffe0004 /* timer 1 control */ |
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252 | #define M_TIC2 0xfffe0008 /* timer 2 initial count */ |
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253 | #define M_TC2 0xfffe000c /* timer 2 control */ |
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254 | #define M_RTIC 0xfffe0010 /* refresh timer */ |
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255 | |
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256 | #ifdef LANGUAGE_C |
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257 | #define TIC1 (*((volatile unsigned long *)M_TIC1)) /* timer1 count */ |
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258 | #define TC1 (*((volatile unsigned long *)M_TC1)) /* timer1 cntrl */ |
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259 | #define TIC2 (*((volatile unsigned long *)M_TIC2)) /* timer2 count */ |
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260 | #define TC2 (*((volatile unsigned long *)M_TC2)) /* timer2 cntrl */ |
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261 | #define RTIC (*((volatile unsigned long *)M_RTIC)) /* refrsh timer */ |
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262 | #endif |
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263 | |
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264 | /* Definitions for counter/timer control register bits */ |
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265 | #define TC_CE 0x00000004 /* count enable */ |
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266 | #define TC_IE 0x00000002 /* interrupt enable */ |
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267 | #define TC_INT 0x00000001 /* interrupt request */ |
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268 | |
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269 | /* lr33000.h */ |
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270 | |
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271 | |
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272 | |
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273 | |
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274 | |
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275 | |
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276 | #define _LR33300_ |
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277 | |
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278 | #define M_SRAM 0xfffe0100 /* SRAM config reg */ |
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279 | #define M_SPEC0 0xfffe0104 |
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280 | #define M_SPEC1 0xfffe0108 |
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281 | #define M_SPEC2 0xfffe010c |
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282 | #define M_SPEC3 0xfffe0110 |
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283 | #define M_DRAM 0xfffe0120 /* DRAM config reg */ |
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284 | |
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285 | #ifdef LANGUAGE_C |
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286 | #define SRAM (*((volatile unsigned long *)M_SRAM)) |
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287 | #define SPEC0 (*((volatile unsigned long *)M_SPEC0)) |
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288 | #define SPEC1 (*((volatile unsigned long *)M_SPEC1)) |
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289 | #define SPEC2 (*((volatile unsigned long *)M_SPEC2)) |
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290 | #define SPEC3 (*((volatile unsigned long *)M_SPEC3)) |
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291 | #define DRAM (*((volatile unsigned long *)M_DRAM)) |
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292 | #endif |
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293 | |
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294 | /* wait-state config registers */ |
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295 | #define SPC_INHIBITMASK (0xf<<24) |
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296 | #define SPC_INHIBITSHFT 24 |
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297 | #define SPC_EXTGNT (1<<23) |
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298 | #define SPC_16WIDE (1<<22) |
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299 | #define SPC_8WIDE (1<<21) |
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300 | #define SPC_PENA (1<<20) |
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301 | #define SPC_CACHED (1<<19) |
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302 | #define SPC_CSDLYMASK (3<<17) |
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303 | #define SPC_CSDLYSHFT 17 |
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304 | #define SPC_BLKENA (1<<16) |
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305 | #define SPC_BLKWAITMASK (7<<13) |
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306 | #define SPC_BLKWAITSHFT 13 |
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307 | #define SPC_RECMASK (63<<7) |
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308 | #define SPC_RECSHFT 7 |
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309 | #define SPC_WAITENA (1<<6) |
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310 | #define SPC_WAITMASK (63<<0) |
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311 | #define SPC_WAITSHFT 0 |
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312 | |
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313 | /* DCR */ |
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314 | #define DRAM_DLP1 (1<<28) |
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315 | #define DRAM_SYNC (1<<27) |
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316 | #define DRAM_SCFG (1<<26) |
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317 | #define DRAM_DMARDY (1<<25) |
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318 | #define DRAM_DMABLKMASK (7<<22) |
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319 | #define DRAM_DMABLKSHFT 22 |
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320 | #define DRAM_DPTHMASK (3<<20) |
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321 | #define DRAM_DPTHSHFT 20 |
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322 | #define DRAM_RDYW (1<<19) |
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323 | #define DRAM_PGSZMASK (7<<16) |
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324 | #define DRAM_PGSZSHFT 16 |
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325 | #define DRAM_PGMW (1<<15) |
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326 | #define DRAM_RFWEMASK (3<<13) |
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327 | #define DRAM_RFWESHFT 13 |
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328 | #define DRAM_RFEN (1<<12) |
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329 | #define DRAM_RDYEN (1<<11) |
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330 | #define DRAM_BFD (1<<10) |
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331 | #define DRAM_PE (1<<9) |
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332 | #define DRAM_RPCMASK (3<<7) |
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333 | #define DRAM_RPCSHFT 7 |
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334 | #define DRAM_RCDMASK (3<<5) |
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335 | #define DRAM_RCDSHFT 5 |
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336 | #define DRAM_CS (1<<4) |
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337 | #define DRAM_CLMASK (7<<1) |
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338 | #define DRAM_CLSHFT 1 |
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339 | #define DRAM_DCE (1<<0) |
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340 | |
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341 | /* _LR33300_ */ |
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342 | |
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343 | |
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344 | |
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345 | |
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346 | |
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347 | |
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348 | |
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349 | #define _ERNIE_CORE_ |
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350 | |
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351 | #define M_BIU 0xfffe0130 |
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352 | |
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353 | #ifdef LANGUAGE_C |
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354 | #define BIU (*((volatile unsigned long *)M_BIU)) |
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355 | |
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356 | #define C0_TAR 6 /* target address register */ |
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357 | #define C0_BDAM 9 /* breakpoint data addr mask */ |
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358 | #define C0_BPCM 11 /* breakpoint instr addr mask */ |
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359 | #else |
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360 | #define C0_TAR $6 /* target address register */ |
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361 | #define C0_BDAM $9 /* breakpoint data addr mask */ |
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362 | #define C0_BPCM $11 /* breakpoint instr addr mask */ |
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363 | #endif |
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364 | |
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365 | /* cause register */ |
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366 | #define CAUSE_BT (1<<30) /* branch taken */ |
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367 | |
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368 | /* BIU */ |
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369 | #define BIU_NOSTR (1<<17) |
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370 | #define BIU_LDSCH (1<<16) |
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371 | #define BIU_BGNT (1<<15) |
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372 | #define BIU_NOPAD (1<<14) |
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373 | #define BIU_RDPRI (1<<13) |
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374 | #define BIU_INTP (1<<12) |
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375 | #define BIU_IS1 (1<<11) |
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376 | #define BIU_IS0 (1<<10) |
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377 | #define BIU_IBLKSZMASK (3<<8) |
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378 | #define BIU_IBLKSZSHFT 8 |
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379 | #define BIU_IBLKSZ2 (0<<BIU_IBLKSZSHFT) |
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380 | #define BIU_IBLKSZ4 (1<<BIU_IBLKSZSHFT) |
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381 | #define BIU_IBLKSZ8 (2<<BIU_IBLKSZSHFT) |
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382 | #define BIU_IBLKSZ16 (3<<BIU_IBLKSZSHFT) |
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383 | #define BIU_DS (1<<7) |
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384 | #define BIU_DS1 (1<<7) |
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385 | #define BIU_DS0 (1<<6) |
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386 | #define BIU_DBLKSZMASK (3<<4) |
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387 | #define BIU_DBLKSZSHFT 4 |
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388 | #define BIU_DBLKSZ2 (0<<BIU_DBLKSZSHFT) |
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389 | #define BIU_DBLKSZ4 (1<<BIU_DBLKSZSHFT) |
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390 | #define BIU_DBLKSZ8 (2<<BIU_DBLKSZSHFT) |
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391 | #define BIU_DBLKSZ16 (3<<BIU_DBLKSZSHFT) |
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392 | #define BIU_RAM (1<<3) |
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393 | #define BIU_TAG (1<<2) |
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394 | #define BIU_INV (1<<1) |
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395 | #define BIU_LOCK (1<<0) |
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396 | |
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397 | /* _ERNIE_CORE_ */ |
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398 | |
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399 | |
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400 | /* Definitions for cache sizes */ |
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401 | |
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402 | #define LR33300_IC_SIZE 0x1000 /* 33300 Inst cache = 4Kbytes */ |
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403 | #define LR33300_DC_SIZE 0x800 /* 33300 Data cache = 2Kbytes */ |
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404 | |
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