1 | /* r3000.h - mips R3k architecture header file */ |
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2 | |
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3 | /* |
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4 | * Copyright 1985-1997 by MIPS Computer Systems, Inc. |
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5 | */ |
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6 | |
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7 | /* |
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8 | modification history |
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9 | -------------------- |
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10 | 01k,17jan96,kkk made MINCACHE 512 (spr# 7556) |
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11 | 01j,13jan96,kkk undid 01i. |
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12 | 01i,18dec96,tam enabled FP exceptions via FP_TASK_STATUS (spr #7665). |
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13 | 01h,13sep93,caf fixed K2SIZE (SPR #1880). |
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14 | 01g,22sep92,rrr added support for c++ |
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15 | 01f,02jun92,ajm the 5.0.5 merge |
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16 | 01e,26may92,rrr the tree shuffle |
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17 | 01d,04oct91,rrr passed through the ansification filter |
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18 | -changed copyright notice |
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19 | 01c,23jul91,ajm changed default fp status register to all exceptions |
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20 | off forcing the user to enable exceptions for signals |
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21 | Enable FPA interrupt to tasks |
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22 | 01b,08jul91,ajm added SR_KUMSK for exception handling |
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23 | 01a,21feb91,ajm written. |
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24 | */ |
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25 | |
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26 | #ifndef __INCr3000h |
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27 | #define __INCr3000h |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif |
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32 | |
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33 | /* |
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34 | * Segment base addresses and sizes |
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35 | */ |
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36 | |
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37 | #define K0BASE 0x80000000 |
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38 | #define K0SIZE 0x20000000 |
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39 | #define K1BASE 0xA0000000 |
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40 | #define K1SIZE 0x20000000 |
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41 | #define K2BASE 0xC0000000 |
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42 | #define K2SIZE 0x40000000 |
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43 | |
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44 | /* |
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45 | * Exception vectors |
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46 | */ |
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47 | |
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48 | #define UT_VEC K0BASE /* utlbmiss vector */ |
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49 | #define E_VEC (K0BASE+0x80) /* exception vector */ |
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50 | #define R_VEC (K1BASE+0x1fc00000) /* reset vector */ |
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51 | |
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52 | /* |
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53 | * Address conversion macros |
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54 | */ |
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55 | |
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56 | #define K0_TO_K1(x) ((unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ |
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57 | #define K1_TO_K0(x) ((unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ |
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58 | #define K0_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ |
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59 | #define K1_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ |
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60 | #define PHYS_TO_K0(x) ((unsigned)(x)|0x80000000) /* physical to kseg0 */ |
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61 | #define PHYS_TO_K1(x) ((unsigned)(x)|0xA0000000) /* physical to kseg1 */ |
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62 | |
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63 | /* |
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64 | * Address predicates |
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65 | */ |
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66 | |
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67 | #define IS_KSEG0(x) ((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE) |
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68 | #define IS_KSEG1(x) ((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE) |
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69 | #define IS_KUSEG(x) ((unsigned)(x) < K0BASE) |
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70 | |
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71 | /* |
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72 | * Cache size constants |
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73 | */ |
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74 | |
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75 | #define MINCACHE +(1*512) /* leading plus for mas's benefit */ |
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76 | #define MAXCACHE +(256*1024) /* leading plus for mas's benefit */ |
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77 | |
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78 | /* |
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79 | * Cause bit definitions |
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80 | */ |
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81 | |
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82 | #define CAUSE_BD 0x80000000 /* Branch delay slot */ |
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83 | #define CAUSE_CEMASK 0x30000000 /* coprocessor error */ |
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84 | #define CAUSE_CESHIFT 28 |
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85 | |
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86 | #define CAUSE_IP8 0x00008000 /* External level 8 pending */ |
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87 | #define CAUSE_IP7 0x00004000 /* External level 7 pending */ |
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88 | #define CAUSE_IP6 0x00002000 /* External level 6 pending */ |
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89 | #define CAUSE_IP5 0x00001000 /* External level 5 pending */ |
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90 | #define CAUSE_IP4 0x00000800 /* External level 4 pending */ |
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91 | #define CAUSE_IP3 0x00000400 /* External level 3 pending */ |
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92 | #define CAUSE_SW2 0x00000200 /* Software level 2 pending */ |
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93 | #define CAUSE_SW1 0x00000100 /* Software level 1 pending */ |
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94 | |
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95 | #define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ |
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96 | #define CAUSE_IPSHIFT 8 |
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97 | |
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98 | #define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ |
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99 | #define CAUSE_EXCSHIFT 2 |
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100 | |
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101 | /* |
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102 | * Status definition bits |
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103 | */ |
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104 | |
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105 | #define SR_CUMASK 0xf0000000 /* coproc usable bits */ |
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106 | #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ |
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107 | #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ |
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108 | #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ |
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109 | #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ |
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110 | #define SR_BEV 0x00400000 /* use boot exception vectors */ |
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111 | #define SR_TS 0x00200000 /* TLB shutdown */ |
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112 | #define SR_PE 0x00100000 /* cache parity error */ |
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113 | #define SR_CM 0x00080000 /* cache miss */ |
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114 | #define SR_PZ 0x00040000 /* cache parity zero */ |
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115 | #define SR_SWC 0x00020000 /* swap cache */ |
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116 | #define SR_ISC 0x00010000 /* Isolate data cache */ |
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117 | #define SR_IMASK 0x0000ff00 /* Interrupt mask */ |
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118 | #define SR_IMASK8 0x00000000 /* mask level 8 */ |
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119 | #define SR_IMASK7 0x00008000 /* mask level 7 */ |
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120 | #define SR_IMASK6 0x0000c000 /* mask level 6 */ |
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121 | #define SR_IMASK5 0x0000e000 /* mask level 5 */ |
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122 | #define SR_IMASK4 0x0000f000 /* mask level 4 */ |
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123 | #define SR_IMASK3 0x0000f800 /* mask level 3 */ |
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124 | #define SR_IMASK2 0x0000fc00 /* mask level 2 */ |
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125 | #define SR_IMASK1 0x0000fe00 /* mask level 1 */ |
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126 | #define SR_IMASK0 0x0000ff00 /* mask level 0 */ |
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127 | |
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128 | #define SR_IBIT8 0x00008000 /* bit level 8 */ |
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129 | #define SR_IBIT7 0x00004000 /* bit level 7 */ |
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130 | #define SR_IBIT6 0x00002000 /* bit level 6 */ |
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131 | #define SR_IBIT5 0x00001000 /* bit level 5 */ |
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132 | #define SR_IBIT4 0x00000800 /* bit level 4 */ |
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133 | #define SR_IBIT3 0x00000400 /* bit level 3 */ |
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134 | #define SR_IBIT2 0x00000200 /* bit level 2 */ |
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135 | #define SR_IBIT1 0x00000100 /* bit level 1 */ |
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136 | |
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137 | #define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ |
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138 | #define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ |
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139 | #define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ |
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140 | #define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ |
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141 | #define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ |
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142 | #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ |
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143 | #define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC) |
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144 | |
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145 | #define SR_IMASKSHIFT 8 |
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146 | |
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147 | /* |
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148 | * fpa definitions |
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149 | */ |
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150 | |
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151 | #define FP_ROUND 0x3 /* r3010 round mode mask */ |
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152 | #define FP_STICKY 0x7c /* r3010 sticky bits mask */ |
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153 | #define FP_ENABLE 0xf80 /* r3010 enable mode mask */ |
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154 | #define FP_EXC 0x3f000 /* r3010 exception mask */ |
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155 | |
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156 | #define FP_ROUND_N 0x0 /* round to nearest */ |
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157 | #define FP_ROUND_Z 0x1 /* round to zero */ |
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158 | #define FP_ROUND_P 0x2 /* round to + infinity */ |
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159 | #define FP_ROUND_M 0x3 /* round to - infinity */ |
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160 | |
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161 | #define FP_STICKY_I 0x4 /* sticky inexact operation */ |
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162 | #define FP_STICKY_U 0x8 /* sticky underflow */ |
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163 | #define FP_STICKY_O 0x10 /* sticky overflow */ |
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164 | #define FP_STICKY_Z 0x20 /* sticky divide by zero */ |
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165 | #define FP_STICKY_V 0x40 /* sticky invalid operation */ |
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166 | |
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167 | #define FP_ENABLE_I 0x80 /* enable inexact operation */ |
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168 | #define FP_ENABLE_U 0x100 /* enable underflow exc */ |
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169 | #define FP_ENABLE_O 0x200 /* enable overflow exc */ |
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170 | #define FP_ENABLE_Z 0x400 /* enable divide by zero exc */ |
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171 | #define FP_ENABLE_V 0x800 /* enable invalid operation exc */ |
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172 | |
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173 | #define FP_EXC_I 0x1000 /* inexact operation */ |
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174 | #define FP_EXC_U 0x2000 /* underflow */ |
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175 | #define FP_EXC_O 0x4000 /* overflow */ |
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176 | #define FP_EXC_Z 0x8000 /* divide by zero */ |
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177 | #define FP_EXC_V 0x10000 /* invalid operation */ |
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178 | #define FP_EXC_E 0x20000 /* unimplemented operation */ |
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179 | |
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180 | #define FP_COND 0x800000 /* condition bit */ |
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181 | |
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182 | #define FP_EXC_SHIFT 12 |
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183 | #define FP_ENABLE_SHIFT 7 |
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184 | #define FP_EXC_MASK (FP_EXC_I|FP_EXC_U|FP_EXC_O|FP_EXC_Z|FP_EXC_V|FP_EXC_E) |
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185 | #define FP_ENABLE_MASK (FP_ENABLE_I|FP_ENABLE_U|FP_ENABLE_O|FP_ENABLE_Z| \ |
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186 | FP_ENABLE_V) |
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187 | #define FP_TASK_STATUS 0x0 /* all FP exceptions are disabled |
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188 | (see fppAlib.s and spr #7665) */ |
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189 | |
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190 | /* |
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191 | * tlb definitions |
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192 | */ |
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193 | |
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194 | #define TLB_ENTRIES 64 |
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195 | #define TLBLO_PFNMASK 0xfffff000 |
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196 | #define TLBLO_PFNSHIFT 12 |
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197 | #define TLBLO_N 0x800 /* non-cacheable */ |
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198 | #define TLBLO_D 0x400 /* writeable */ |
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199 | #define TLBLO_V 0x200 /* valid bit */ |
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200 | #define TLBHI_VPNMASK 0xfffff000 |
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201 | #define TLBHI_VPNSHIFT 12 |
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202 | #define TLBHI_PIDMASK 0xfc0 |
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203 | #define TLBHI_PIDSHIFT 6 |
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204 | #define TLBHI_NPID 64 |
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205 | #define TLBINX_PROBE 0x80000000 |
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206 | #define TLBINX_INXMASK 0x00003f00 |
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207 | #define TLBINX_INXSHIFT 8 |
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208 | #define TLBRAND_RANDMASK 0x00003f00 |
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209 | #define TLBRAND_RANDSHIFT 8 |
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210 | #define TLBCTXT_BASEMASK 0xffe00000 |
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211 | #define TLBCTXT_BASESHIFT 21 |
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212 | #define TLBCTXT_VPNMASK 0x001ffffc |
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213 | #define TLBCTXT_VPNSHIFT 2 |
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214 | |
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215 | /* |
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216 | * Coprocessor 0 operations |
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217 | */ |
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218 | |
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219 | #define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */ |
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220 | #define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */ |
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221 | #define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */ |
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222 | #define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */ |
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223 | #define C0_RFE 0x10 /* restore for exception */ |
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224 | |
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225 | #ifdef __cplusplus |
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226 | } |
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227 | #endif |
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228 | |
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229 | #endif /* __INCr3000h */ |
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