source: rtems/c/src/lib/libbsp/mips/genmongoosev/include/r3000.h @ 3299388d

4.104.114.84.95
Last change on this file since 3299388d was 2276d255, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 2, 2002 at 7:28:13 PM

2001-02-01 Greg Menke <gregory.menke@…>

  • include/lr33000.h, include/lr330x0.h, include/r3000.h, start/mg5.h: New files missed in previous commit.
  • timer/timer.c: Use rtems/bspIo.h not just bspIo.h.
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/* r3000.h - mips R3k architecture header file */
2
3/*
4* Copyright 1985-1997 by MIPS Computer Systems, Inc.
5*/
6
7/*
8modification history
9--------------------
1001k,17jan96,kkk  made MINCACHE 512 (spr# 7556)
1101j,13jan96,kkk  undid 01i.
1201i,18dec96,tam  enabled FP exceptions via FP_TASK_STATUS (spr #7665).
1301h,13sep93,caf  fixed K2SIZE (SPR #1880).
1401g,22sep92,rrr  added support for c++
1501f,02jun92,ajm  the 5.0.5 merge
1601e,26may92,rrr  the tree shuffle
1701d,04oct91,rrr  passed through the ansification filter
18                  -changed copyright notice
1901c,23jul91,ajm  changed default fp status register to all exceptions
20                  off forcing the user to enable exceptions for signals
21                  Enable FPA interrupt to tasks
2201b,08jul91,ajm  added SR_KUMSK for exception handling
2301a,21feb91,ajm  written.
24*/
25
26#ifndef __INCr3000h
27#define __INCr3000h
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/*
34* Segment base addresses and sizes
35*/
36
37#define K0BASE          0x80000000
38#define K0SIZE          0x20000000
39#define K1BASE          0xA0000000
40#define K1SIZE          0x20000000
41#define K2BASE          0xC0000000
42#define K2SIZE          0x40000000
43
44/*
45* Exception vectors
46*/
47
48#define UT_VEC          K0BASE                  /* utlbmiss vector */
49#define E_VEC           (K0BASE+0x80)           /* exception vector */
50#define R_VEC           (K1BASE+0x1fc00000)     /* reset vector */
51
52/*
53 * Address conversion macros
54 */
55
56#define K0_TO_K1(x)     ((unsigned)(x)|0xA0000000)      /* kseg0 to kseg1 */
57#define K1_TO_K0(x)     ((unsigned)(x)&0x9FFFFFFF)      /* kseg1 to kseg0 */
58#define K0_TO_PHYS(x)   ((unsigned)(x)&0x1FFFFFFF)      /* kseg0 to physical */
59#define K1_TO_PHYS(x)   ((unsigned)(x)&0x1FFFFFFF)      /* kseg1 to physical */
60#define PHYS_TO_K0(x)   ((unsigned)(x)|0x80000000)      /* physical to kseg0 */
61#define PHYS_TO_K1(x)   ((unsigned)(x)|0xA0000000)      /* physical to kseg1 */
62
63/*
64* Address predicates
65*/
66
67#define IS_KSEG0(x)     ((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE)
68#define IS_KSEG1(x)     ((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE)
69#define IS_KUSEG(x)     ((unsigned)(x) < K0BASE)
70
71/*
72* Cache size constants
73*/
74
75#define MINCACHE        +(1*512)        /* leading plus for mas's benefit */
76#define MAXCACHE        +(256*1024)     /* leading plus for mas's benefit */
77
78/*
79* Cause bit definitions
80*/
81
82#define CAUSE_BD        0x80000000      /* Branch delay slot */
83#define CAUSE_CEMASK    0x30000000      /* coprocessor error */
84#define CAUSE_CESHIFT   28
85
86#define CAUSE_IP8       0x00008000      /* External level 8 pending */
87#define CAUSE_IP7       0x00004000      /* External level 7 pending */
88#define CAUSE_IP6       0x00002000      /* External level 6 pending */
89#define CAUSE_IP5       0x00001000      /* External level 5 pending */
90#define CAUSE_IP4       0x00000800      /* External level 4 pending */
91#define CAUSE_IP3       0x00000400      /* External level 3 pending */
92#define CAUSE_SW2       0x00000200      /* Software level 2 pending */
93#define CAUSE_SW1       0x00000100      /* Software level 1 pending */
94
95#define CAUSE_IPMASK    0x0000FF00      /* Pending interrupt mask */
96#define CAUSE_IPSHIFT   8
97
98#define CAUSE_EXCMASK   0x0000003C      /* Cause code bits */
99#define CAUSE_EXCSHIFT  2
100
101/*
102* Status definition bits
103*/
104
105#define SR_CUMASK       0xf0000000      /* coproc usable bits */
106#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
107#define SR_CU2          0x40000000      /* Coprocessor 2 usable */
108#define SR_CU1          0x20000000      /* Coprocessor 1 usable */
109#define SR_CU0          0x10000000      /* Coprocessor 0 usable */
110#define SR_BEV          0x00400000      /* use boot exception vectors */
111#define SR_TS           0x00200000      /* TLB shutdown */
112#define SR_PE           0x00100000      /* cache parity error */
113#define SR_CM           0x00080000      /* cache miss */
114#define SR_PZ           0x00040000      /* cache parity zero */
115#define SR_SWC          0x00020000      /* swap cache */
116#define SR_ISC          0x00010000      /* Isolate data cache */
117#define SR_IMASK        0x0000ff00      /* Interrupt mask */
118#define SR_IMASK8       0x00000000      /* mask level 8 */
119#define SR_IMASK7       0x00008000      /* mask level 7 */
120#define SR_IMASK6       0x0000c000      /* mask level 6 */
121#define SR_IMASK5       0x0000e000      /* mask level 5 */
122#define SR_IMASK4       0x0000f000      /* mask level 4 */
123#define SR_IMASK3       0x0000f800      /* mask level 3 */
124#define SR_IMASK2       0x0000fc00      /* mask level 2 */
125#define SR_IMASK1       0x0000fe00      /* mask level 1 */
126#define SR_IMASK0       0x0000ff00      /* mask level 0 */
127
128#define SR_IBIT8        0x00008000      /* bit level 8 */
129#define SR_IBIT7        0x00004000      /* bit level 7 */
130#define SR_IBIT6        0x00002000      /* bit level 6 */
131#define SR_IBIT5        0x00001000      /* bit level 5 */
132#define SR_IBIT4        0x00000800      /* bit level 4 */
133#define SR_IBIT3        0x00000400      /* bit level 3 */
134#define SR_IBIT2        0x00000200      /* bit level 2 */
135#define SR_IBIT1        0x00000100      /* bit level 1 */
136
137#define SR_KUO          0x00000020      /* old kernel/user, 0 => k, 1 => u */
138#define SR_IEO          0x00000010      /* old interrupt enable, 1 => enable */
139#define SR_KUP          0x00000008      /* prev kernel/user, 0 => k, 1 => u */
140#define SR_IEP          0x00000004      /* prev interrupt enable, 1 => enable */
141#define SR_KUC          0x00000002      /* cur kernel/user, 0 => k, 1 => u */
142#define SR_IEC          0x00000001      /* cur interrupt enable, 1 => enable */
143#define SR_KUMSK        (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC)
144
145#define SR_IMASKSHIFT   8
146
147/*
148* fpa definitions
149*/
150
151#define FP_ROUND        0x3             /* r3010 round mode mask */
152#define FP_STICKY       0x7c            /* r3010 sticky bits mask */
153#define FP_ENABLE       0xf80           /* r3010 enable mode mask */
154#define FP_EXC          0x3f000         /* r3010 exception mask */
155
156#define FP_ROUND_N      0x0             /* round to nearest */
157#define FP_ROUND_Z      0x1             /* round to zero */
158#define FP_ROUND_P      0x2             /* round to + infinity */
159#define FP_ROUND_M      0x3             /* round to - infinity */
160
161#define FP_STICKY_I     0x4             /* sticky inexact operation */
162#define FP_STICKY_U     0x8             /* sticky underflow */
163#define FP_STICKY_O     0x10            /* sticky overflow */
164#define FP_STICKY_Z     0x20            /* sticky divide by zero */
165#define FP_STICKY_V     0x40            /* sticky invalid operation */
166
167#define FP_ENABLE_I     0x80            /* enable inexact operation */
168#define FP_ENABLE_U     0x100           /* enable underflow exc  */
169#define FP_ENABLE_O     0x200           /* enable overflow exc  */
170#define FP_ENABLE_Z     0x400           /* enable divide by zero exc  */
171#define FP_ENABLE_V     0x800           /* enable invalid operation exc  */
172
173#define FP_EXC_I        0x1000          /* inexact operation */
174#define FP_EXC_U        0x2000          /* underflow */
175#define FP_EXC_O        0x4000          /* overflow */
176#define FP_EXC_Z        0x8000          /* divide by zero */
177#define FP_EXC_V        0x10000         /* invalid operation */
178#define FP_EXC_E        0x20000         /* unimplemented operation */
179
180#define FP_COND         0x800000        /* condition bit */
181
182#define FP_EXC_SHIFT    12
183#define FP_ENABLE_SHIFT 7
184#define FP_EXC_MASK     (FP_EXC_I|FP_EXC_U|FP_EXC_O|FP_EXC_Z|FP_EXC_V|FP_EXC_E)
185#define FP_ENABLE_MASK  (FP_ENABLE_I|FP_ENABLE_U|FP_ENABLE_O|FP_ENABLE_Z| \
186                         FP_ENABLE_V)
187#define FP_TASK_STATUS  0x0             /* all FP exceptions  are disabled
188                                           (see fppAlib.s and spr #7665) */
189
190/*
191* tlb definitions
192*/
193
194#define TLB_ENTRIES             64
195#define TLBLO_PFNMASK           0xfffff000
196#define TLBLO_PFNSHIFT          12
197#define TLBLO_N                 0x800           /* non-cacheable */
198#define TLBLO_D                 0x400           /* writeable */
199#define TLBLO_V                 0x200           /* valid bit */
200#define TLBHI_VPNMASK           0xfffff000
201#define TLBHI_VPNSHIFT          12
202#define TLBHI_PIDMASK           0xfc0
203#define TLBHI_PIDSHIFT          6
204#define TLBHI_NPID              64
205#define TLBINX_PROBE            0x80000000
206#define TLBINX_INXMASK          0x00003f00
207#define TLBINX_INXSHIFT         8
208#define TLBRAND_RANDMASK        0x00003f00
209#define TLBRAND_RANDSHIFT       8
210#define TLBCTXT_BASEMASK        0xffe00000
211#define TLBCTXT_BASESHIFT       21
212#define TLBCTXT_VPNMASK         0x001ffffc
213#define TLBCTXT_VPNSHIFT        2
214
215/*
216* Coprocessor 0 operations
217*/
218
219#define C0_READI  0x1           /* read ITLB entry addressed by C0_INDEX */
220#define C0_WRITEI 0x2           /* write ITLB entry addressed by C0_INDEX */
221#define C0_WRITER 0x6           /* write ITLB entry addressed by C0_RAND */
222#define C0_PROBE  0x8           /* probe for ITLB entry addressed by TLBHI */
223#define C0_RFE    0x10          /* restore for exception */
224
225#ifdef __cplusplus
226}
227#endif
228
229#endif /* __INCr3000h */
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