source: rtems/c/src/lib/libbsp/mips/genmongoosev/include/lr333x0.h @ 3299388d

4.104.114.84.95
Last change on this file since 3299388d was 2276d255, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 2, 2002 at 7:28:13 PM

2001-02-01 Greg Menke <gregory.menke@…>

  • include/lr33000.h, include/lr330x0.h, include/r3000.h, start/mg5.h: New files missed in previous commit.
  • timer/timer.c: Use rtems/bspIo.h not just bspIo.h.
  • Property mode set to 100644
File size: 8.3 KB
Line 
1/* lr333x0.h - LSI LR333x0 CPU header */
2
3/* $Id$ */
4
5#ifndef __INClr333x0h
6#define __INClr333x0h
7
8#ifdef __cplusplus
9extern "C" {
10#endif
11
12#ifdef _ASMLANGUAGE
13#define C0_BPC  $3              /* breakpoint on instr */
14#define C0_BDA  $5              /* breakpoint on data */
15#define C0_TAR  $6              /* target address register */
16#define C0_DCIC $7              /* cache control */
17#define C0_BDAM $9              /* breakpoint data addr mask */
18#define C0_BPCM $11             /* breakpoint instr addr mask */
19#else
20IMPORT  int sysICsize;          /* inst cache size defined in BSP */
21IMPORT  int sysDCsize;          /* data cache size defined in BSP */
22IMPORT  BOOL sysICset0;         /* inst cache set 0 present ? */
23#endif /* _ASMLANGUAGE */
24
25#define DEBUG_VECT      0x00000040
26#define K0_DEBUG_VECT   (K0BASE+DEBUG_VECT)
27#define K1_DEBUG_VECT   (K1BASE+DEBUG_VECT)
28
29/* Define register addresses */
30
31#define M_TIC1          0xfffe0000      /* timer 1 initial count   */
32#define M_TC1           0xfffe0004      /* timer 1 control         */
33#define M_TIC2          0xfffe0008      /* timer 2 initial count   */
34#define M_TC2           0xfffe000c      /* timer 2 control         */
35#define M_RTIC          0xfffe0010      /* refresh timer           */
36#define M_SRAM          0xfffe0100      /* SRAM config reg */
37#define M_SPEC0         0xfffe0104
38#define M_SPEC1         0xfffe0108
39#define M_SPEC2         0xfffe010c
40#define M_SPEC3         0xfffe0110
41#define M_DRAM          0xfffe0120      /* DRAM configuration      */
42#define M_BIU           0xfffe0130      /* BIU/cache configuration */
43
44/* Definitions for Debug and Cache Invalidate control (DCIC) register bits */
45
46#define DCIC_TR         0x80000000      /* Trap enable */
47#define DCIC_UD         0x40000000      /* User debug enable */
48#define DCIC_KD         0x20000000      /* Kernel debug enable */
49#define DCIC_TE         0x10000000      /* Trace enable */
50#define DCIC_DW         0x08000000      /* Enable data breakpoints on write */
51#define DCIC_DR         0x04000000      /* Enable data breakpoints on read */
52#define DCIC_DAE        0x02000000      /* Enable data addresss breakpoints */
53#define DCIC_PCE        0x01000000      /* Enable instruction breakpoints */
54#define DCIC_DE         0x00800000      /* Debug enable */
55#define DCIC_T          0x00000020      /* Trace, set by CPU */
56#define DCIC_W          0x00000010      /* Write reference, set by CPU */
57#define DCIC_R          0x00000008      /* Read reference, set by CPU */
58#define DCIC_DA         0x00000004      /* Data address, set by CPU */
59#define DCIC_PC         0x00000002      /* Program counter, set by CPU */
60#define DCIC_DB         0x00000001      /* Debug, set by CPU */
61
62/* Definitions for counter/timer control register bits */
63
64#define TC_CE           0x00000004      /* count enable */
65#define TC_IE           0x00000002      /* interrupt enable (1 == enable) */
66#define TC_INT          0x00000001      /* interrupt acknowlege (0 == ack) */
67
68/* Definitions for Wait-state configuration register bits */
69
70#define SPC_INHIBITSHFT 24              /* Inhibit shift count */
71#define SPC_EXTGNT      0x00800000      /* External data ready */
72#define SPC_16WIDE      0x00400000      /* 16-bit wide memory */
73#define SPC_8WIDE       0x00200000      /* 8-bit wide memory */
74#define SPC_PENA        0x00100000      /* Parity enable */
75#define SPC_CACHED      0x00080000      /* Cache data */
76#define SPC_CSDLY_3     0x00060000      /* Select delay, 3 cycles */
77#define SPC_CSDLY_2     0x00040000      /* Select delay, 2 cycles */
78#define SPC_CSDLY_1     0x00020000      /* Select delay, 1 cycles */
79#define SPC_CSDLY_0     0x00000000      /* Select delay, 0 cycles */
80#define SPC_BLKENA      0x00010000      /* Block enable */
81#define SPC_BLKWAIT_7   0x0000e000      /* Block delay, 7 cycles */
82#define SPC_BLKWAIT_6   0x0000c000      /* Block delay, 6 cycles */
83#define SPC_BLKWAIT_5   0x0000a000      /* Block delay, 5 cycles */
84#define SPC_BLKWAIT_4   0x00008000      /* Block delay, 4 cycles */
85#define SPC_BLKWAIT_3   0x00006000      /* Block delay, 3 cycles */
86#define SPC_BLKWAIT_2   0x00004000      /* Block delay, 2 cycles */
87#define SPC_BLKWAIT_1   0x00002000      /* Block delay, 1 cycles */
88#define SPC_BLKWAIT_0   0x00000000      /* Block delay, 0 cycles */
89#define SPC_RECSHFT     7               /* Recovery time shift count */
90#define SPC_WAITENA     0x00000040      /* Wait-state generator enable */
91#define SPC_WAITSHFT    0               /* Wait shift count */
92
93/* Definitions for DRAM configuration register bits */
94
95#define DRAM_DLP1       0x10000000      /* Data latch in phase 1 */
96#define DRAM_SYNC       0x08000000      /* Sunchronous DRAM mode */
97#define DRAM_SCFG       0x04000000      /* Synchronous Configuration mode */
98#define DRAM_DMARDY     0x02000000      /* DMA ready */
99#define DRAM_DMABLK_64  0x01400000      /* DMA block refill size, 64 words */
100#define DRAM_DMABLK_32  0x01000000      /* DMA block refill size, 32 words */
101#define DRAM_DMABLK_16  0x00c00000      /* DMA block refill size, 16 words */
102#define DRAM_DMABLK_8   0x00800000      /* DMA block refill size, 8 words */
103#define DRAM_DMABLK_4   0x00400000      /* DMA block refill size, 4 words */
104#define DRAM_DMABLK_2   0x00000000      /* DMA block refill size, 2 words */
105#define DRAM_DPTH_8     0x00300000      /* CAS ready depth, 8 per cycle */
106#define DRAM_DPTH_4     0x00200000      /* CAS ready depth, 4 per cycle */
107#define DRAM_DPTH_2     0x00100000      /* CAS ready depth, 2 per cycle */
108#define DRAM_DPTH_1     0x00000000      /* CAS ready depth, 1 per cycle */
109#define DRAM_RDYW       0x00080000      /* Ready Wait */
110#define DRAM_PGSZ_2K    0x00070000      /* Page size, 2K words */
111#define DRAM_PGSZ_1K    0x00060000      /* Page size, 1K words */
112#define DRAM_PGSZ_512   0x00050000      /* Page size, 512 words */
113#define DRAM_PGSZ_256   0x00040000      /* Page size, 256 words */
114#define DRAM_PGSZ_128   0x00030000      /* Page size, 128 words */
115#define DRAM_PGSZ_64    0x00020000      /* Page size, 64 words */
116#define DRAM_PGSZ_32    0x00010000      /* Page size, 32 words */
117#define DRAM_PGSZ_16    0x00000000      /* Page size, 16 words */
118#define DRAM_PGMW       0x00008000      /* Page mode write enable */
119#define DRAM_RFWE_0     0x00004000      /* Refresh write enable mode, bit 1 */
120#define DRAM_RFWE_1     0x00002000      /* Refresh write enable mode, bit 0 */
121#define DRAM_RFEN       0x00001000      /* Internal refresh enable */
122#define DRAM_RDYEN      0x00000800      /* Internal ready generation */
123#define DRAM_BFD        0x00000400      /* Block fetch disable */
124#define DRAM_PE         0x00000200      /* Parity checking enable */
125#define DRAM_RPC_3      0x00000180      /* RAS precharge, 3 */
126#define DRAM_RPC_2      0x00000100      /* RAS precharge, 2 */
127#define DRAM_RPC_1      0x00000080      /* RAS precharge, 1 */
128#define DRAM_RPC_0      0x00000000      /* RAS precharge, 0 */
129#define DRAM_RCD_3      0x00000060      /* RAS to CAS delay, 3 */
130#define DRAM_RCD_2      0x00000040      /* RAS to CAS delay, 2 */
131#define DRAM_RCD_1      0x00000020      /* RAS to CAS delay, 1 */
132#define DRAM_RCD_0      0x00000000      /* RAS to CAS delay, 0 */
133#define DRAM_CS         0x00000010      /* CAS short */
134#define DRAM_CL_8_5     0x0000000f      /* CAS length, 8.5 cycles */
135#define DRAM_CL_7_5     0x0000000c      /* CAS length, 7.5 cycles*/
136#define DRAM_CL_6_5     0x0000000a      /* CAS length, 6.5 cycles */
137#define DRAM_CL_5_5     0x00000008      /* CAS length, 5.5 cycles */
138#define DRAM_CL_4_5     0x00000006      /* CAS length, 4.5 cycles */
139#define DRAM_CL_3_5     0x00000004      /* CAS length, 3.5 cycles*/
140#define DRAM_CL_2_5     0x00000002      /* CAS length, 2.5 cycles */
141#define DRAM_CL_1_5     0x00000000      /* CAS length, 1.5 cycles */
142#define DRAM_DCE        0x00000001      /* DRAM controller enable */
143
144/* Definitions for BIU/cache configuration register bits */
145
146#define BIU_NOSTR       0x00020000      /* no instruction streaming */
147#define BIU_LDSCH       0x00010000      /* enable load scheduling */
148#define BIU_BGNT        0x00008000      /* enable bus grant */
149#define BIU_NOPAD       0x00004000      /* no wait state */
150#define BIU_RDPRI       0x00002000      /* enable read priority */
151#define BIU_INTP        0x00001000      /* interrupt polarity */
152#define BIU_IS1         0x00000800      /* enable Inst cache, set 1 */
153#define BIU_IS0         0x00000400      /* enable Inst cache, set 0 */
154#define BIU_IBLKSZ_16   0x00000300      /* Inst cache fill sz = 16 words */
155#define BIU_IBLKSZ_8    0x00000200      /* Inst cache fill sz = 8 words */
156#define BIU_IBLKSZ_4    0x00000100      /* Inst cache fill sz = 4 words */
157#define BIU_IBLKSZ_2    0x00000000      /* Inst cache fill sz = 2 words */
158#define BIU_DS          0x00000080      /* enable Data cache */
159#define BIU_DBLKSZ_16   0x00000030      /* Data cache fill sz = 16 words */
160#define BIU_DBLKSZ_8    0x00000020      /* Data cache fill sz = 8 words */
161#define BIU_DBLKSZ_4    0x00000010      /* Data cache fill sz = 4 words */
162#define BIU_DBLKSZ_2    0x00000000      /* Data cache fill sz = 2 words */
163#define BIU_RAM         0x00000008      /* scratchpad RAM */
164#define BIU_TAG         0x00000004      /* tag test mode */
165#define BIU_INV         0x00000002      /* invalidate mode */
166#define BIU_LOCK        0x00000001      /* lock mode */
167
168/* Definitions for cache sizes */
169
170#define LR33300_IC_SIZE 0x1000          /* 33300 Inst cache = 4Kbytes */
171#define LR33310_IC_SIZE 0x1000          /* 33310 Inst cache = 4Kbytes */
172                                        /*     Note: each set is 4Kbytes! */
173
174#define LR33300_DC_SIZE 0x800           /* 33300 Data cache = 2Kbytes */
175#define LR33310_DC_SIZE 0x1000          /* 33310 Data cache = 4Kbytes */
176
177
178#ifdef __cplusplus
179}
180#endif
181
182#endif /* __INClr333x0h */
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