[2276d255] | 1 | /* lr333x0.h - LSI LR333x0 CPU header */ |
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| 2 | |
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| 3 | /* $Id$ */ |
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| 4 | |
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| 5 | #ifndef __INClr333x0h |
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| 6 | #define __INClr333x0h |
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| 7 | |
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| 8 | #ifdef __cplusplus |
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| 9 | extern "C" { |
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| 10 | #endif |
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| 11 | |
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| 12 | #ifdef _ASMLANGUAGE |
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| 13 | #define C0_BPC $3 /* breakpoint on instr */ |
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| 14 | #define C0_BDA $5 /* breakpoint on data */ |
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| 15 | #define C0_TAR $6 /* target address register */ |
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| 16 | #define C0_DCIC $7 /* cache control */ |
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| 17 | #define C0_BDAM $9 /* breakpoint data addr mask */ |
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| 18 | #define C0_BPCM $11 /* breakpoint instr addr mask */ |
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| 19 | #else |
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| 20 | IMPORT int sysICsize; /* inst cache size defined in BSP */ |
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| 21 | IMPORT int sysDCsize; /* data cache size defined in BSP */ |
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| 22 | IMPORT BOOL sysICset0; /* inst cache set 0 present ? */ |
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| 23 | #endif /* _ASMLANGUAGE */ |
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| 24 | |
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| 25 | #define DEBUG_VECT 0x00000040 |
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| 26 | #define K0_DEBUG_VECT (K0BASE+DEBUG_VECT) |
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| 27 | #define K1_DEBUG_VECT (K1BASE+DEBUG_VECT) |
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| 28 | |
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| 29 | /* Define register addresses */ |
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| 30 | |
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| 31 | #define M_TIC1 0xfffe0000 /* timer 1 initial count */ |
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| 32 | #define M_TC1 0xfffe0004 /* timer 1 control */ |
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| 33 | #define M_TIC2 0xfffe0008 /* timer 2 initial count */ |
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| 34 | #define M_TC2 0xfffe000c /* timer 2 control */ |
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| 35 | #define M_RTIC 0xfffe0010 /* refresh timer */ |
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| 36 | #define M_SRAM 0xfffe0100 /* SRAM config reg */ |
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| 37 | #define M_SPEC0 0xfffe0104 |
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| 38 | #define M_SPEC1 0xfffe0108 |
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| 39 | #define M_SPEC2 0xfffe010c |
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| 40 | #define M_SPEC3 0xfffe0110 |
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| 41 | #define M_DRAM 0xfffe0120 /* DRAM configuration */ |
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| 42 | #define M_BIU 0xfffe0130 /* BIU/cache configuration */ |
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| 43 | |
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| 44 | /* Definitions for Debug and Cache Invalidate control (DCIC) register bits */ |
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| 45 | |
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| 46 | #define DCIC_TR 0x80000000 /* Trap enable */ |
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| 47 | #define DCIC_UD 0x40000000 /* User debug enable */ |
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| 48 | #define DCIC_KD 0x20000000 /* Kernel debug enable */ |
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| 49 | #define DCIC_TE 0x10000000 /* Trace enable */ |
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| 50 | #define DCIC_DW 0x08000000 /* Enable data breakpoints on write */ |
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| 51 | #define DCIC_DR 0x04000000 /* Enable data breakpoints on read */ |
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| 52 | #define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */ |
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| 53 | #define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */ |
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| 54 | #define DCIC_DE 0x00800000 /* Debug enable */ |
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| 55 | #define DCIC_T 0x00000020 /* Trace, set by CPU */ |
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| 56 | #define DCIC_W 0x00000010 /* Write reference, set by CPU */ |
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| 57 | #define DCIC_R 0x00000008 /* Read reference, set by CPU */ |
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| 58 | #define DCIC_DA 0x00000004 /* Data address, set by CPU */ |
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| 59 | #define DCIC_PC 0x00000002 /* Program counter, set by CPU */ |
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| 60 | #define DCIC_DB 0x00000001 /* Debug, set by CPU */ |
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| 61 | |
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| 62 | /* Definitions for counter/timer control register bits */ |
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| 63 | |
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| 64 | #define TC_CE 0x00000004 /* count enable */ |
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| 65 | #define TC_IE 0x00000002 /* interrupt enable (1 == enable) */ |
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| 66 | #define TC_INT 0x00000001 /* interrupt acknowlege (0 == ack) */ |
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| 67 | |
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| 68 | /* Definitions for Wait-state configuration register bits */ |
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| 69 | |
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| 70 | #define SPC_INHIBITSHFT 24 /* Inhibit shift count */ |
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| 71 | #define SPC_EXTGNT 0x00800000 /* External data ready */ |
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| 72 | #define SPC_16WIDE 0x00400000 /* 16-bit wide memory */ |
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| 73 | #define SPC_8WIDE 0x00200000 /* 8-bit wide memory */ |
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| 74 | #define SPC_PENA 0x00100000 /* Parity enable */ |
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| 75 | #define SPC_CACHED 0x00080000 /* Cache data */ |
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| 76 | #define SPC_CSDLY_3 0x00060000 /* Select delay, 3 cycles */ |
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| 77 | #define SPC_CSDLY_2 0x00040000 /* Select delay, 2 cycles */ |
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| 78 | #define SPC_CSDLY_1 0x00020000 /* Select delay, 1 cycles */ |
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| 79 | #define SPC_CSDLY_0 0x00000000 /* Select delay, 0 cycles */ |
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| 80 | #define SPC_BLKENA 0x00010000 /* Block enable */ |
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| 81 | #define SPC_BLKWAIT_7 0x0000e000 /* Block delay, 7 cycles */ |
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| 82 | #define SPC_BLKWAIT_6 0x0000c000 /* Block delay, 6 cycles */ |
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| 83 | #define SPC_BLKWAIT_5 0x0000a000 /* Block delay, 5 cycles */ |
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| 84 | #define SPC_BLKWAIT_4 0x00008000 /* Block delay, 4 cycles */ |
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| 85 | #define SPC_BLKWAIT_3 0x00006000 /* Block delay, 3 cycles */ |
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| 86 | #define SPC_BLKWAIT_2 0x00004000 /* Block delay, 2 cycles */ |
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| 87 | #define SPC_BLKWAIT_1 0x00002000 /* Block delay, 1 cycles */ |
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| 88 | #define SPC_BLKWAIT_0 0x00000000 /* Block delay, 0 cycles */ |
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| 89 | #define SPC_RECSHFT 7 /* Recovery time shift count */ |
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| 90 | #define SPC_WAITENA 0x00000040 /* Wait-state generator enable */ |
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| 91 | #define SPC_WAITSHFT 0 /* Wait shift count */ |
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| 92 | |
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| 93 | /* Definitions for DRAM configuration register bits */ |
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| 94 | |
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| 95 | #define DRAM_DLP1 0x10000000 /* Data latch in phase 1 */ |
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| 96 | #define DRAM_SYNC 0x08000000 /* Sunchronous DRAM mode */ |
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| 97 | #define DRAM_SCFG 0x04000000 /* Synchronous Configuration mode */ |
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| 98 | #define DRAM_DMARDY 0x02000000 /* DMA ready */ |
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| 99 | #define DRAM_DMABLK_64 0x01400000 /* DMA block refill size, 64 words */ |
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| 100 | #define DRAM_DMABLK_32 0x01000000 /* DMA block refill size, 32 words */ |
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| 101 | #define DRAM_DMABLK_16 0x00c00000 /* DMA block refill size, 16 words */ |
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| 102 | #define DRAM_DMABLK_8 0x00800000 /* DMA block refill size, 8 words */ |
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| 103 | #define DRAM_DMABLK_4 0x00400000 /* DMA block refill size, 4 words */ |
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| 104 | #define DRAM_DMABLK_2 0x00000000 /* DMA block refill size, 2 words */ |
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| 105 | #define DRAM_DPTH_8 0x00300000 /* CAS ready depth, 8 per cycle */ |
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| 106 | #define DRAM_DPTH_4 0x00200000 /* CAS ready depth, 4 per cycle */ |
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| 107 | #define DRAM_DPTH_2 0x00100000 /* CAS ready depth, 2 per cycle */ |
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| 108 | #define DRAM_DPTH_1 0x00000000 /* CAS ready depth, 1 per cycle */ |
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| 109 | #define DRAM_RDYW 0x00080000 /* Ready Wait */ |
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| 110 | #define DRAM_PGSZ_2K 0x00070000 /* Page size, 2K words */ |
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| 111 | #define DRAM_PGSZ_1K 0x00060000 /* Page size, 1K words */ |
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| 112 | #define DRAM_PGSZ_512 0x00050000 /* Page size, 512 words */ |
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| 113 | #define DRAM_PGSZ_256 0x00040000 /* Page size, 256 words */ |
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| 114 | #define DRAM_PGSZ_128 0x00030000 /* Page size, 128 words */ |
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| 115 | #define DRAM_PGSZ_64 0x00020000 /* Page size, 64 words */ |
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| 116 | #define DRAM_PGSZ_32 0x00010000 /* Page size, 32 words */ |
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| 117 | #define DRAM_PGSZ_16 0x00000000 /* Page size, 16 words */ |
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| 118 | #define DRAM_PGMW 0x00008000 /* Page mode write enable */ |
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| 119 | #define DRAM_RFWE_0 0x00004000 /* Refresh write enable mode, bit 1 */ |
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| 120 | #define DRAM_RFWE_1 0x00002000 /* Refresh write enable mode, bit 0 */ |
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| 121 | #define DRAM_RFEN 0x00001000 /* Internal refresh enable */ |
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| 122 | #define DRAM_RDYEN 0x00000800 /* Internal ready generation */ |
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| 123 | #define DRAM_BFD 0x00000400 /* Block fetch disable */ |
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| 124 | #define DRAM_PE 0x00000200 /* Parity checking enable */ |
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| 125 | #define DRAM_RPC_3 0x00000180 /* RAS precharge, 3 */ |
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| 126 | #define DRAM_RPC_2 0x00000100 /* RAS precharge, 2 */ |
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| 127 | #define DRAM_RPC_1 0x00000080 /* RAS precharge, 1 */ |
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| 128 | #define DRAM_RPC_0 0x00000000 /* RAS precharge, 0 */ |
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| 129 | #define DRAM_RCD_3 0x00000060 /* RAS to CAS delay, 3 */ |
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| 130 | #define DRAM_RCD_2 0x00000040 /* RAS to CAS delay, 2 */ |
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| 131 | #define DRAM_RCD_1 0x00000020 /* RAS to CAS delay, 1 */ |
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| 132 | #define DRAM_RCD_0 0x00000000 /* RAS to CAS delay, 0 */ |
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| 133 | #define DRAM_CS 0x00000010 /* CAS short */ |
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| 134 | #define DRAM_CL_8_5 0x0000000f /* CAS length, 8.5 cycles */ |
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| 135 | #define DRAM_CL_7_5 0x0000000c /* CAS length, 7.5 cycles*/ |
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| 136 | #define DRAM_CL_6_5 0x0000000a /* CAS length, 6.5 cycles */ |
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| 137 | #define DRAM_CL_5_5 0x00000008 /* CAS length, 5.5 cycles */ |
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| 138 | #define DRAM_CL_4_5 0x00000006 /* CAS length, 4.5 cycles */ |
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| 139 | #define DRAM_CL_3_5 0x00000004 /* CAS length, 3.5 cycles*/ |
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| 140 | #define DRAM_CL_2_5 0x00000002 /* CAS length, 2.5 cycles */ |
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| 141 | #define DRAM_CL_1_5 0x00000000 /* CAS length, 1.5 cycles */ |
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| 142 | #define DRAM_DCE 0x00000001 /* DRAM controller enable */ |
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| 143 | |
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| 144 | /* Definitions for BIU/cache configuration register bits */ |
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| 145 | |
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| 146 | #define BIU_NOSTR 0x00020000 /* no instruction streaming */ |
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| 147 | #define BIU_LDSCH 0x00010000 /* enable load scheduling */ |
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| 148 | #define BIU_BGNT 0x00008000 /* enable bus grant */ |
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| 149 | #define BIU_NOPAD 0x00004000 /* no wait state */ |
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| 150 | #define BIU_RDPRI 0x00002000 /* enable read priority */ |
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| 151 | #define BIU_INTP 0x00001000 /* interrupt polarity */ |
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| 152 | #define BIU_IS1 0x00000800 /* enable Inst cache, set 1 */ |
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| 153 | #define BIU_IS0 0x00000400 /* enable Inst cache, set 0 */ |
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| 154 | #define BIU_IBLKSZ_16 0x00000300 /* Inst cache fill sz = 16 words */ |
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| 155 | #define BIU_IBLKSZ_8 0x00000200 /* Inst cache fill sz = 8 words */ |
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| 156 | #define BIU_IBLKSZ_4 0x00000100 /* Inst cache fill sz = 4 words */ |
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| 157 | #define BIU_IBLKSZ_2 0x00000000 /* Inst cache fill sz = 2 words */ |
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| 158 | #define BIU_DS 0x00000080 /* enable Data cache */ |
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| 159 | #define BIU_DBLKSZ_16 0x00000030 /* Data cache fill sz = 16 words */ |
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| 160 | #define BIU_DBLKSZ_8 0x00000020 /* Data cache fill sz = 8 words */ |
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| 161 | #define BIU_DBLKSZ_4 0x00000010 /* Data cache fill sz = 4 words */ |
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| 162 | #define BIU_DBLKSZ_2 0x00000000 /* Data cache fill sz = 2 words */ |
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| 163 | #define BIU_RAM 0x00000008 /* scratchpad RAM */ |
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| 164 | #define BIU_TAG 0x00000004 /* tag test mode */ |
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| 165 | #define BIU_INV 0x00000002 /* invalidate mode */ |
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| 166 | #define BIU_LOCK 0x00000001 /* lock mode */ |
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| 167 | |
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| 168 | /* Definitions for cache sizes */ |
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| 169 | |
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| 170 | #define LR33300_IC_SIZE 0x1000 /* 33300 Inst cache = 4Kbytes */ |
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| 171 | #define LR33310_IC_SIZE 0x1000 /* 33310 Inst cache = 4Kbytes */ |
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| 172 | /* Note: each set is 4Kbytes! */ |
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| 173 | |
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| 174 | #define LR33300_DC_SIZE 0x800 /* 33300 Data cache = 2Kbytes */ |
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| 175 | #define LR33310_DC_SIZE 0x1000 /* 33310 Data cache = 4Kbytes */ |
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| 176 | |
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| 177 | |
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| 178 | #ifdef __cplusplus |
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| 179 | } |
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| 180 | #endif |
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| 181 | |
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| 182 | #endif /* __INClr333x0h */ |
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