[2276d255] | 1 | /* lr33000.h - LSI LR33000 CPU header */ |
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| 2 | |
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| 3 | /* $Id$ */ |
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| 4 | |
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| 5 | /* |
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| 6 | modification history |
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| 7 | -------------------- |
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| 8 | 01c,22sep92,rrr added support for c++ |
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| 9 | 01b,20apr92,ajm added CR_DCAS for ethernet support |
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| 10 | 01a,10feb92,ajm written for FCS |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef __INClr33000h |
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| 14 | #define __INClr33000h |
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| 15 | |
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| 16 | #ifdef __cplusplus |
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| 17 | extern "C" { |
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| 18 | #endif |
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| 19 | |
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| 20 | #ifdef _ASMLANGUAGE |
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| 21 | #define C0_DCIC $7 /* cache control */ |
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| 22 | #define C0_BPC $3 /* breakpoint on instr */ |
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| 23 | #define C0_BDA $5 /* breakpoint on data */ |
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| 24 | #endif /* _ASMLANGUAGE */ |
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| 25 | |
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| 26 | #define DEBUG_VECT 0x00000040 |
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| 27 | #define K0_DEBUG_VECT (K0BASE+DEBUG_VECT) |
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| 28 | #define K1_DEBUG_VECT (K1BASE+DEBUG_VECT) |
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| 29 | |
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| 30 | /* definitions for Debug and Cache Invalidate control (DCIC) register bits */ |
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| 31 | #define DCIC_TR 0x80000000 /* Trap enable */ |
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| 32 | #define DCIC_UD 0x40000000 /* User debug enable */ |
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| 33 | #define DCIC_KD 0x20000000 /* Kernel debug enable */ |
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| 34 | #define DCIC_TE 0x10000000 /* Trace enable */ |
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| 35 | #define DCIC_DW 0x08000000 /* Enable data breakpoints on write */ |
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| 36 | #define DCIC_DR 0x04000000 /* Enable data breakpoints on read */ |
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| 37 | #define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */ |
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| 38 | #define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */ |
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| 39 | #define DCIC_DE 0x00800000 /* Debug enable */ |
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| 40 | #define DCIC_DL 0x00008000 /* Data cache line invalidate */ |
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| 41 | #define DCIC_IL 0x00004000 /* Instruction cache line invalidate */ |
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| 42 | #define DCIC_D 0x00002000 /* Data cache invalidate enable */ |
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| 43 | #define DCIC_I 0x00001000 /* Instr. cache invalidate enable */ |
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| 44 | #define DCIC_T 0x00000020 /* Trace, set by CPU */ |
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| 45 | #define DCIC_W 0x00000010 /* Write reference, set by CPU */ |
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| 46 | #define DCIC_R 0x00000008 /* Read reference, set by CPU */ |
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| 47 | #define DCIC_DA 0x00000004 /* Data address, set by CPU */ |
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| 48 | #define DCIC_PC 0x00000002 /* Program counter, set by CPU */ |
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| 49 | #define DCIC_DB 0x00000001 /* Debug, set by CPU */ |
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| 50 | |
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| 51 | /* Define counter/timer register addresses */ |
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| 52 | #define M_TIC1 0xfffe0000 /* timer 1 initial count */ |
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| 53 | #define M_TC1 0xfffe0004 /* timer 1 control */ |
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| 54 | #define M_TIC2 0xfffe0008 /* timer 2 initial count */ |
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| 55 | #define M_TC2 0xfffe000c /* timer 2 control */ |
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| 56 | #define M_RTIC 0xfffe0010 /* refresh timer */ |
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| 57 | #define M_CFGREG 0xfffe0020 /* configuration reg */ |
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| 58 | |
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| 59 | /* Definitions for counter/timer control register bits */ |
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| 60 | #define TC_CE 0x00000004 /* count enable */ |
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| 61 | #define TC_IE 0x00000002 /* interrupt enable (1 == enable) */ |
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| 62 | #define TC_INT 0x00000001 /* interrupt acknowlege (0 == ack) */ |
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| 63 | #define TCNT_MASK 0x00ffffff /* 24 bit timer mask */ |
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| 64 | |
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| 65 | /* Definitions for Configuration register bits */ |
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| 66 | #define CR_ICDISABLE 0x00800000 /* Instruction cache disable */ |
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| 67 | #define CR_DCDISABLE 0x00400000 /* Data cache disable */ |
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| 68 | #define CR_IBLK_2 0x00000000 /* Instruction cache block size */ |
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| 69 | #define CR_IBLK_4 0x00100000 /* Instruction cache block size */ |
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| 70 | #define CR_IBLK_8 0x00200000 /* Instruction cache block size */ |
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| 71 | #define CR_IBLK_16 0x00300000 /* Instruction cache block size */ |
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| 72 | #define CR_IBLKMSK 0x00300000 /* Instruction cache block size */ |
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| 73 | #define CR_DBLK_2 0x00000000 /* Data cache block size */ |
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| 74 | #define CR_DBLK_4 0x00040000 /* Data cache block size */ |
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| 75 | #define CR_DBLK_8 0x00080000 /* Data cache block size */ |
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| 76 | #define CR_DBLK_16 0x000c0000 /* Data cache block size */ |
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| 77 | #define CR_DBLKMSK 0x000c0000 /* Data cache block size */ |
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| 78 | #define CR_IODIS 0x00020000 /* Disable DRDY for I/O addresses */ |
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| 79 | #define CR_IOWAITSHFT 13 /* I/O wait states */ |
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| 80 | #define CR_PDIS 0x00001000 /* Disable DRDY for PROM addresses */ |
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| 81 | #define CR_PWAITSHFT 8 /* PROM wait states */ |
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| 82 | #define CR_DCAS 0x00000080 /* Define # cycles of DCAS */ |
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| 83 | #define CR_DPEN 0x00000040 /* Enable parity check for DRAM */ |
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| 84 | #define CR_RDYGEN 0x00000020 /* Disable DRDY for DRAM addresses */ |
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| 85 | #define CR_BLKFDIS 0x00000010 /* Disable DRAM block refill */ |
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| 86 | #define CR_RFSHEN 0x00000008 /* Enable refresh generator */ |
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| 87 | #define CR_RASPCHG 0x00000004 /* Define RAS precharge */ |
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| 88 | #define CR_CASLNTH 0x00000002 /* Define CAS active time */ |
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| 89 | #define CR_DRAMEN 0x00000001 /* Enable DRAM controller */ |
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| 90 | #define CR_PWT(x) ((x) << 8) /* memory wait states */ |
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| 91 | #define CR_IOWT(x) ((x) << 13) /* io wait states */ |
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| 92 | |
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| 93 | #define LR33000_DSIZE 0x400 /* Data cache = 1Kbytes */ |
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| 94 | #define LR33000_ISIZE 0x2000 /* Instructrion cache = 8Kbytes */ |
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| 95 | |
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| 96 | #ifdef __cplusplus |
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| 97 | } |
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| 98 | #endif |
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| 99 | |
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| 100 | #endif /* __INClr33000h */ |
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