1 | /* |
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2 | * Au1x00 ethernet driver |
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3 | * |
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4 | * Copyright (c) 2005 by Cogent Computer Systems |
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5 | * Written by Jay Monkman <jtm@lopingdog.com> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #include <rtems.h> |
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15 | #include <rtems/rtems_bsdnet.h> |
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16 | #include <bsp.h> |
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17 | #include <rtems/bspIo.h> |
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18 | #include <libcpu/au1x00.h> |
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19 | |
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20 | #include <stdio.h> |
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21 | #include <string.h> |
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22 | |
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23 | #include <errno.h> |
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24 | #include <rtems/error.h> |
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25 | |
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26 | #include <sys/param.h> |
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27 | #include <sys/mbuf.h> |
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28 | #include <sys/socket.h> |
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29 | #include <sys/sockio.h> |
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30 | |
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31 | #include <net/if.h> |
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32 | |
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33 | #include <netinet/in.h> |
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34 | #include <netinet/if_ether.h> |
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35 | |
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36 | #include <assert.h> |
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37 | |
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38 | #define NUM_IFACES 1 |
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39 | #define NUM_TX_DMA_BUFS 4 |
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40 | #define NUM_RX_DMA_BUFS 4 |
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41 | |
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42 | /* RTEMS event used to start tx daemon. */ |
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43 | #define START_TX_EVENT RTEMS_EVENT_1 |
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44 | /* RTEMS event used to start rx daemon. */ |
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45 | #define START_RX_EVENT RTEMS_EVENT_2 |
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46 | |
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47 | rtems_isr au1x00_emac_isr(rtems_vector_number vector); |
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48 | |
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49 | #define TX_BUF_SIZE 2048 |
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50 | |
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51 | char tx_buf_base[(4 * TX_BUF_SIZE) + 32]; |
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52 | |
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53 | volatile int wait_count; |
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54 | /* |
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55 | * Hardware-specific storage |
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56 | */ |
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57 | typedef struct |
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58 | { |
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59 | /* |
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60 | * Connection to networking code |
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61 | * This entry *must* be the first in the sonic_softc structure. |
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62 | */ |
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63 | struct arpcom arpcom; |
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64 | |
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65 | /* |
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66 | * Interrupt vector |
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67 | */ |
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68 | rtems_vector_number vector; |
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69 | |
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70 | /* |
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71 | * Indicates configuration |
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72 | */ |
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73 | int acceptBroadcast; |
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74 | |
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75 | /* |
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76 | * Tasks waiting for interrupts |
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77 | */ |
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78 | rtems_id rx_daemon_tid; |
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79 | rtems_id tx_daemon_tid; |
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80 | |
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81 | /* |
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82 | * Buffers |
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83 | */ |
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84 | au1x00_macdma_rx_t *rx_dma; |
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85 | au1x00_macdma_tx_t *tx_dma; |
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86 | int rx_head; |
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87 | int rx_tail; |
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88 | int tx_head; |
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89 | int tx_tail; |
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90 | struct mbuf *rx_mbuf[NUM_RX_DMA_BUFS]; |
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91 | |
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92 | unsigned char *tx_buf[4]; |
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93 | |
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94 | /* |
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95 | * register addresses |
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96 | */ |
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97 | uint32_t ctrl_regs; |
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98 | uint32_t *en_reg; |
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99 | uint32_t int_mask; |
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100 | uint32_t int_ctrlr; |
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101 | |
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102 | /* |
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103 | * device |
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104 | */ |
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105 | int unitnumber; |
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106 | |
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107 | /* |
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108 | * Statistics |
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109 | */ |
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110 | unsigned long interrupts; |
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111 | unsigned long rx_interrupts; |
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112 | unsigned long tx_interrupts; |
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113 | unsigned long rx_missed; |
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114 | unsigned long rx_bcast; |
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115 | unsigned long rx_mcast; |
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116 | unsigned long rx_unsupp; |
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117 | unsigned long rx_ctrl; |
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118 | unsigned long rx_len_err; |
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119 | unsigned long rx_crc_err; |
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120 | unsigned long rx_dribble; |
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121 | unsigned long rx_mii_err; |
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122 | unsigned long rx_collision; |
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123 | unsigned long rx_too_long; |
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124 | unsigned long rx_runt; |
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125 | unsigned long rx_watchdog; |
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126 | unsigned long rx_pkts; |
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127 | unsigned long rx_dropped; |
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128 | |
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129 | unsigned long tx_deferred; |
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130 | unsigned long tx_underrun; |
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131 | unsigned long tx_aborted; |
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132 | unsigned long tx_pkts; |
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133 | } au1x00_emac_softc_t; |
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134 | |
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135 | static au1x00_emac_softc_t softc[NUM_IFACES]; |
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136 | |
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137 | |
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138 | /* function prototypes */ |
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139 | int rtems_au1x00_emac_attach (struct rtems_bsdnet_ifconfig *config, |
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140 | int attaching); |
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141 | void au1x00_emac_init(void *arg); |
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142 | void au1x00_emac_init_hw(au1x00_emac_softc_t *sc); |
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143 | void au1x00_emac_start(struct ifnet *ifp); |
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144 | void au1x00_emac_stop (au1x00_emac_softc_t *sc); |
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145 | void au1x00_emac_tx_daemon (void *arg); |
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146 | void au1x00_emac_rx_daemon (void *arg); |
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147 | void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m); |
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148 | void au1x00_emac_stats (au1x00_emac_softc_t *sc); |
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149 | static int au1x00_emac_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_t data); |
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150 | static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val); |
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151 | static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val); |
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152 | static void mii_init(au1x00_emac_softc_t *sc); |
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153 | |
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154 | static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val) |
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155 | { |
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156 | /* wait for the interface to get unbusy */ |
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157 | while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) { |
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158 | continue; |
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159 | } |
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160 | |
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161 | /* write to address 0 - we only support address 0 */ |
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162 | AU1X00_MAC_MIIDATA(sc->ctrl_regs) = val; |
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163 | AU1X00_MAC_MIICTRL(sc->ctrl_regs) = (((reg & 0x1f) << 6) | |
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164 | AU1X00_MAC_MIICTRL_MW); |
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165 | au_sync(); |
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166 | |
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167 | /* wait for it to complete */ |
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168 | while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) { |
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169 | continue; |
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170 | } |
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171 | } |
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172 | |
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173 | static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val) |
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174 | { |
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175 | /* wait for the interface to get unbusy */ |
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176 | while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) { |
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177 | continue; |
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178 | } |
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179 | |
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180 | /* write to address 0 - we only support address 0 */ |
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181 | AU1X00_MAC_MIICTRL(sc->ctrl_regs) = ((reg & 0x1f) << 6); |
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182 | au_sync(); |
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183 | |
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184 | /* wait for it to complete */ |
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185 | while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) { |
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186 | continue; |
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187 | } |
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188 | *val = AU1X00_MAC_MIIDATA(sc->ctrl_regs); |
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189 | } |
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190 | |
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191 | static void mii_init(au1x00_emac_softc_t *sc) |
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192 | { |
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193 | uint16_t data; |
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194 | |
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195 | mii_write(sc, 0, 0x8000); /* reset */ |
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196 | do { |
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197 | mii_read(sc, 0, &data); |
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198 | } while (data & 0x8000); |
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199 | |
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200 | mii_write(sc, 0, 0x3200); /* reset autonegotiation */ |
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201 | mii_write(sc, 17, 0xffc0); /* setup LEDs */ |
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202 | |
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203 | } |
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204 | |
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205 | |
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206 | |
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207 | int rtems_au1x00_emac_attach ( |
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208 | struct rtems_bsdnet_ifconfig *config, |
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209 | int attaching |
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210 | ) |
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211 | { |
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212 | struct ifnet *ifp; |
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213 | int mtu; |
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214 | int unitnumber; |
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215 | char *unitname; |
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216 | static au1x00_emac_softc_t *sc; |
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217 | |
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218 | /* |
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219 | * Parse driver name |
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220 | */ |
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221 | if ((unitnumber = rtems_bsdnet_parse_driver_name (config, &unitname)) < 0) |
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222 | return 0; |
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223 | |
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224 | /* |
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225 | * Is driver free? |
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226 | */ |
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227 | if (unitnumber > NUM_IFACES) { |
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228 | printf ("Bad AU1X00 EMAC unit number.\n"); |
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229 | return 0; |
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230 | } |
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231 | |
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232 | sc = &softc[unitnumber]; |
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233 | |
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234 | ifp = &sc->arpcom.ac_if; |
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235 | if (ifp->if_softc != NULL) { |
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236 | printf ("Driver already in use.\n"); |
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237 | return 0; |
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238 | } |
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239 | |
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240 | /* |
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241 | * zero out the control structure |
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242 | */ |
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243 | |
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244 | memset((void *)sc, 0, sizeof(*sc)); |
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245 | |
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246 | sc->unitnumber = unitnumber; |
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247 | sc->int_ctrlr = AU1X00_IC0_ADDR; |
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248 | |
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249 | if (unitnumber == 0) { |
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250 | sc->ctrl_regs = AU1100_MAC0_ADDR; |
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251 | sc->en_reg = (void *)(AU1100_MACEN_ADDR + 0); |
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252 | |
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253 | sc->tx_dma = (void *)(AU1X00_MACDMA0_ADDR + 0x000); |
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254 | sc->rx_dma = (void *)(AU1X00_MACDMA0_ADDR + 0x100); |
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255 | sc->int_mask = AU1X00_IC_IRQ_MAC0; |
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256 | } else { |
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257 | printk("Unknown network device: %d\n", unitnumber); |
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258 | return 0; |
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259 | } |
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260 | |
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261 | /* If the ethernet controller is already set up, read the MAC address */ |
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262 | if ((*sc->en_reg & 0x33) == 0x33) { |
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263 | sc->arpcom.ac_enaddr[5] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) & |
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264 | 0xff); |
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265 | sc->arpcom.ac_enaddr[4] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 0) & |
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266 | 0xff); |
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267 | sc->arpcom.ac_enaddr[3] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 24) & |
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268 | 0xff); |
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269 | sc->arpcom.ac_enaddr[2] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 16) & |
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270 | 0xff); |
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271 | sc->arpcom.ac_enaddr[1] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) & |
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272 | 0xff); |
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273 | sc->arpcom.ac_enaddr[0] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) & |
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274 | 0xff); |
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275 | } else { |
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276 | /* It's not set up yet, so we set a MAC address */ |
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277 | sc->arpcom.ac_enaddr[5] = 0x05; |
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278 | sc->arpcom.ac_enaddr[4] = 0xc0; |
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279 | sc->arpcom.ac_enaddr[3] = 0x50; |
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280 | sc->arpcom.ac_enaddr[2] = 0x31; |
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281 | sc->arpcom.ac_enaddr[1] = 0x23; |
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282 | sc->arpcom.ac_enaddr[0] = 0x00; |
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283 | } |
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284 | |
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285 | |
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286 | if (config->mtu) { |
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287 | mtu = config->mtu; |
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288 | } else { |
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289 | mtu = ETHERMTU; |
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290 | } |
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291 | |
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292 | sc->acceptBroadcast = !config->ignore_broadcast; |
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293 | |
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294 | /* |
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295 | * Set up network interface values |
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296 | */ |
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297 | ifp->if_softc = sc; |
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298 | ifp->if_unit = unitnumber; |
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299 | ifp->if_name = unitname; |
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300 | ifp->if_mtu = mtu; |
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301 | ifp->if_init = au1x00_emac_init; |
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302 | ifp->if_ioctl = au1x00_emac_ioctl; |
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303 | ifp->if_start = au1x00_emac_start; |
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304 | ifp->if_output = ether_output; |
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305 | ifp->if_flags = IFF_BROADCAST; |
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306 | if (ifp->if_snd.ifq_maxlen == 0) { |
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307 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
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308 | } |
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309 | |
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310 | /* |
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311 | * Attach the interface |
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312 | */ |
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313 | if_attach (ifp); |
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314 | ether_ifattach (ifp); |
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315 | return 1; |
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316 | } |
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317 | |
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318 | void au1x00_emac_init(void *arg) |
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319 | { |
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320 | au1x00_emac_softc_t *sc = arg; |
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321 | struct ifnet *ifp = &sc->arpcom.ac_if; |
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322 | |
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323 | /* |
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324 | *This is for stuff that only gets done once (au1x00_emac_init() |
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325 | * gets called multiple times |
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326 | */ |
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327 | if (sc->tx_daemon_tid == 0) |
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328 | { |
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329 | /* Set up EMAC hardware */ |
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330 | au1x00_emac_init_hw(sc); |
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331 | |
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332 | |
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333 | /* install the interrupt handler */ |
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334 | if (sc->unitnumber == 0) { |
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335 | set_vector(au1x00_emac_isr, AU1X00_IRQ_MAC0, 1); |
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336 | } else { |
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337 | set_vector(au1x00_emac_isr, AU1X00_IRQ_MAC1, 1); |
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338 | } |
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339 | AU1X00_IC_MASKCLR(sc->int_ctrlr) = sc->int_mask; |
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340 | au_sync(); |
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341 | |
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342 | /* set src bit */ |
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343 | AU1X00_IC_SRCSET(sc->int_ctrlr) = sc->int_mask; |
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344 | |
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345 | /* high level */ |
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346 | AU1X00_IC_CFG0SET(sc->int_ctrlr) = sc->int_mask; |
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347 | AU1X00_IC_CFG1CLR(sc->int_ctrlr) = sc->int_mask; |
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348 | AU1X00_IC_CFG2SET(sc->int_ctrlr) = sc->int_mask; |
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349 | |
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350 | /* assign to request 0 - negative logic */ |
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351 | AU1X00_IC_ASSIGNSET(sc->int_ctrlr) = sc->int_mask; |
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352 | au_sync(); |
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353 | |
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354 | /* Start driver tasks */ |
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355 | sc->tx_daemon_tid = rtems_bsdnet_newproc("ENTx", |
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356 | 4096, |
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357 | au1x00_emac_tx_daemon, |
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358 | sc); |
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359 | |
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360 | sc->rx_daemon_tid = rtems_bsdnet_newproc("ENRx", |
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361 | 4096, |
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362 | au1x00_emac_rx_daemon, |
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363 | sc); |
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364 | |
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365 | |
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366 | } |
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367 | /* EMAC doesn't support promiscuous, so ignore requests */ |
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368 | if (ifp->if_flags & IFF_PROMISC) |
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369 | printf ("Warning - AU1X00 EMAC doesn't support Promiscuous Mode!\n"); |
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370 | |
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371 | /* |
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372 | * Tell the world that we're running. |
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373 | */ |
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374 | ifp->if_flags |= IFF_RUNNING; |
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375 | |
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376 | /* |
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377 | * start tx, rx |
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378 | */ |
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379 | AU1X00_MAC_CONTROL(sc->ctrl_regs) |= (AU1X00_MAC_CTRL_TE | |
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380 | AU1X00_MAC_CTRL_RE); |
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381 | au_sync(); |
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382 | |
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383 | |
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384 | } /* au1x00_emac_init() */ |
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385 | |
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386 | void au1x00_emac_init_hw(au1x00_emac_softc_t *sc) |
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387 | { |
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388 | int i; |
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389 | struct mbuf *m; |
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390 | struct ifnet *ifp = &sc->arpcom.ac_if; |
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391 | |
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392 | /* reset the MAC */ |
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393 | *sc->en_reg = 0x40; |
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394 | au_sync(); |
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395 | for (i = 0; i < 10000; i++) { |
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396 | continue; |
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397 | } |
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398 | |
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399 | /* *sc->en_reg = AU1X00_MAC_EN_CE; */ |
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400 | *sc->en_reg = 41; |
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401 | au_sync(); |
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402 | for (i = 0; i < 10000; i++) { |
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403 | continue; |
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404 | } |
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405 | |
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406 | /* |
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407 | *sc->en_reg = (AU1X00_MAC_EN_CE | |
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408 | AU1X00_MAC_EN_E2 | |
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409 | AU1X00_MAC_EN_E1 | |
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410 | AU1X00_MAC_EN_E0); |
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411 | */ |
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412 | *sc->en_reg = 0x33; |
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413 | au_sync(); |
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414 | mii_init(sc); |
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415 | |
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416 | /* set the mac address */ |
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417 | AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) = ((sc->arpcom.ac_enaddr[5] << 8) | |
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418 | (sc->arpcom.ac_enaddr[4] << 0)); |
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419 | AU1X00_MAC_ADDRLOW(sc->ctrl_regs) = ((sc->arpcom.ac_enaddr[3] << 24) | |
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420 | (sc->arpcom.ac_enaddr[2] << 16) | |
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421 | (sc->arpcom.ac_enaddr[1] << 8) | |
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422 | (sc->arpcom.ac_enaddr[0] << 0)); |
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423 | |
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424 | |
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425 | /* get the MAC address from the chip */ |
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426 | sc->arpcom.ac_enaddr[5] = (AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) & 0xff; |
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427 | sc->arpcom.ac_enaddr[4] = (AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 0) & 0xff; |
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428 | sc->arpcom.ac_enaddr[3] = (AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 24) & 0xff; |
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429 | sc->arpcom.ac_enaddr[2] = (AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 16) & 0xff; |
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430 | sc->arpcom.ac_enaddr[1] = (AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) & 0xff; |
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431 | sc->arpcom.ac_enaddr[0] = (AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) & 0xff; |
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432 | |
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433 | printk("Setting mac_control to 0x%x\n", |
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434 | (AU1X00_MAC_CTRL_F | |
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435 | AU1X00_MAC_CTRL_PM | |
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436 | AU1X00_MAC_CTRL_RA | |
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437 | AU1X00_MAC_CTRL_DO | |
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438 | AU1X00_MAC_CTRL_EM)); |
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439 | |
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440 | AU1X00_MAC_CONTROL(sc->ctrl_regs) = (AU1X00_MAC_CTRL_F | /* full duplex */ |
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441 | AU1X00_MAC_CTRL_PM | /* pass mcast */ |
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442 | AU1X00_MAC_CTRL_RA | /* recv all */ |
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443 | AU1X00_MAC_CTRL_DO | /* disable own */ |
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444 | AU1X00_MAC_CTRL_EM); /* Big endian */ |
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445 | au_sync(); |
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446 | printk("mac_control was set to 0x%x\n", AU1X00_MAC_CONTROL(sc->ctrl_regs)); |
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447 | printk("mac_control addr is 0x%x\n", &AU1X00_MAC_CONTROL(sc->ctrl_regs)); |
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448 | |
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449 | /* initialize our receive buffer descriptors */ |
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450 | for (i = 0; i < NUM_RX_DMA_BUFS; i++) { |
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451 | MGETHDR(m, M_WAIT, MT_DATA); |
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452 | MCLGET(m, M_WAIT); |
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453 | |
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454 | m->m_pkthdr.rcvif = ifp; |
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455 | m->m_nextpkt = 0; |
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456 | |
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457 | /* |
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458 | * The receive buffer must be aligned with a cache line |
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459 | * boundary. |
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460 | */ |
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461 | if (mtod(m, uint32_t) & 0x1f) { |
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462 | uint32_t *p = mtod(m, uint32_t *); |
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463 | *p = (mtod(m, uint32_t) + 0x1f) & 0x1f; |
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464 | } |
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465 | sc->rx_dma[i].addr = (mtod(m, uint32_t) & ~0xe0000000); |
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466 | sc->rx_mbuf[i] = m; |
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467 | } |
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468 | |
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469 | /* Initialize transmit buffer descriptors */ |
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470 | for (i = 0; i < NUM_TX_DMA_BUFS; i++) { |
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471 | sc->tx_dma[i].addr = 0; |
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472 | } |
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473 | |
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474 | /* initialize the transmit buffers */ |
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475 | sc->tx_buf[0] = (void *)((((int)&tx_buf_base[0]) + 0x1f) & ~0x1f); |
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476 | sc->tx_buf[1] = (void *)(((int)sc->tx_buf[0]) + TX_BUF_SIZE); |
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477 | sc->tx_buf[2] = (void *)(((int)sc->tx_buf[1]) + TX_BUF_SIZE); |
---|
478 | sc->tx_buf[3] = (void *)(((int)sc->tx_buf[2]) + TX_BUF_SIZE); |
---|
479 | |
---|
480 | sc->rx_head = (sc->rx_dma[0].addr >> 2) & 0x3; |
---|
481 | sc->rx_tail = (sc->rx_dma[0].addr >> 2) & 0x3; |
---|
482 | sc->tx_head = (sc->tx_dma[0].addr >> 2) & 0x3; |
---|
483 | sc->tx_tail = (sc->tx_dma[0].addr >> 2) & 0x3; |
---|
484 | |
---|
485 | for (i = 0; i < NUM_RX_DMA_BUFS; i++) { |
---|
486 | sc->rx_dma[i].addr |= AU1X00_MAC_DMA_RXADDR_EN; |
---|
487 | } |
---|
488 | |
---|
489 | } /* au1x00_emac_init_hw() */ |
---|
490 | |
---|
491 | void au1x00_emac_start(struct ifnet *ifp) |
---|
492 | { |
---|
493 | au1x00_emac_softc_t *sc = ifp->if_softc; |
---|
494 | |
---|
495 | rtems_event_send(sc->tx_daemon_tid, START_TX_EVENT); |
---|
496 | ifp->if_flags |= IFF_OACTIVE; |
---|
497 | } |
---|
498 | |
---|
499 | void au1x00_emac_stop (au1x00_emac_softc_t *sc) |
---|
500 | { |
---|
501 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
502 | |
---|
503 | ifp->if_flags &= ~IFF_RUNNING; |
---|
504 | |
---|
505 | /* |
---|
506 | * Stop the transmitter and receiver. |
---|
507 | */ |
---|
508 | |
---|
509 | /* Disable TX/RX */ |
---|
510 | AU1X00_MAC_CONTROL(sc->ctrl_regs) &= ~(AU1X00_MAC_CTRL_TE | |
---|
511 | AU1X00_MAC_CTRL_RE); |
---|
512 | au_sync(); |
---|
513 | } |
---|
514 | |
---|
515 | /* |
---|
516 | * Driver tx daemon |
---|
517 | */ |
---|
518 | void au1x00_emac_tx_daemon (void *arg) |
---|
519 | { |
---|
520 | au1x00_emac_softc_t *sc = (au1x00_emac_softc_t *)arg; |
---|
521 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
522 | struct mbuf *m; |
---|
523 | rtems_event_set events; |
---|
524 | uint32_t ic_base; /* interrupt controller */ |
---|
525 | |
---|
526 | ic_base = AU1X00_IC0_ADDR; |
---|
527 | |
---|
528 | /* turn on interrupt, then wait for one */ |
---|
529 | if (sc->unitnumber == 0) { |
---|
530 | AU1X00_IC_MASKSET(ic_base) = AU1X00_IC_IRQ_MAC0; |
---|
531 | } else { |
---|
532 | AU1X00_IC_MASKSET(ic_base) = AU1X00_IC_IRQ_MAC1; |
---|
533 | } |
---|
534 | au_sync(); |
---|
535 | |
---|
536 | for (;;) |
---|
537 | { |
---|
538 | rtems_bsdnet_event_receive( |
---|
539 | START_TX_EVENT, |
---|
540 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
---|
541 | RTEMS_NO_TIMEOUT, |
---|
542 | &events); |
---|
543 | |
---|
544 | /* Send packets till queue is empty */ |
---|
545 | for (;;) |
---|
546 | { |
---|
547 | /* Get the next mbuf chain to transmit. */ |
---|
548 | IF_DEQUEUE(&ifp->if_snd, m); |
---|
549 | if (!m) |
---|
550 | break; |
---|
551 | |
---|
552 | sc->tx_pkts++; |
---|
553 | au1x00_emac_sendpacket (ifp, m); |
---|
554 | } |
---|
555 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
556 | } |
---|
557 | } |
---|
558 | |
---|
559 | /* |
---|
560 | * Driver rx daemon |
---|
561 | */ |
---|
562 | void au1x00_emac_rx_daemon (void *arg) |
---|
563 | { |
---|
564 | au1x00_emac_softc_t *sc = (au1x00_emac_softc_t *)arg; |
---|
565 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
566 | struct mbuf *m; |
---|
567 | struct ether_header *eh; |
---|
568 | rtems_event_set events; |
---|
569 | uint32_t status; |
---|
570 | |
---|
571 | while (1) { |
---|
572 | rtems_bsdnet_event_receive( |
---|
573 | START_RX_EVENT, |
---|
574 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
---|
575 | RTEMS_NO_TIMEOUT, |
---|
576 | &events); |
---|
577 | |
---|
578 | /* while there are packets to receive */ |
---|
579 | |
---|
580 | while (!(sc->rx_dma[sc->rx_head].addr & (AU1X00_MAC_DMA_RXADDR_DN | |
---|
581 | AU1X00_MAC_DMA_RXADDR_EN))) { |
---|
582 | status = sc->rx_dma[sc->rx_head].stat; |
---|
583 | if (status & AU1X00_MAC_DMA_RXSTAT_MI) { |
---|
584 | sc->rx_missed++; |
---|
585 | } |
---|
586 | if (status & AU1X00_MAC_DMA_RXSTAT_BF) { |
---|
587 | sc->rx_bcast++; |
---|
588 | } |
---|
589 | if (status & AU1X00_MAC_DMA_RXSTAT_MF) { |
---|
590 | sc->rx_mcast++; |
---|
591 | } |
---|
592 | if (status & AU1X00_MAC_DMA_RXSTAT_UC) { |
---|
593 | sc->rx_unsupp++; |
---|
594 | } |
---|
595 | if (status & AU1X00_MAC_DMA_RXSTAT_CF) { |
---|
596 | sc->rx_ctrl++; |
---|
597 | } |
---|
598 | if (status & AU1X00_MAC_DMA_RXSTAT_LE) { |
---|
599 | sc->rx_len_err++; |
---|
600 | } |
---|
601 | if (status & AU1X00_MAC_DMA_RXSTAT_CR) { |
---|
602 | sc->rx_crc_err++; |
---|
603 | } |
---|
604 | if (status & AU1X00_MAC_DMA_RXSTAT_DB) { |
---|
605 | sc->rx_dribble++; |
---|
606 | } |
---|
607 | if (status & AU1X00_MAC_DMA_RXSTAT_ME) { |
---|
608 | sc->rx_mii_err++; |
---|
609 | } |
---|
610 | if (status & AU1X00_MAC_DMA_RXSTAT_CS) { |
---|
611 | sc->rx_collision++; |
---|
612 | } |
---|
613 | if (status & AU1X00_MAC_DMA_RXSTAT_FL) { |
---|
614 | sc->rx_too_long++; |
---|
615 | } |
---|
616 | if (status & AU1X00_MAC_DMA_RXSTAT_RF) { |
---|
617 | sc->rx_runt++; |
---|
618 | } |
---|
619 | if (status & AU1X00_MAC_DMA_RXSTAT_WT) { |
---|
620 | sc->rx_watchdog++; |
---|
621 | } |
---|
622 | |
---|
623 | /* If no errrors, accept packet */ |
---|
624 | if ((status & (AU1X00_MAC_DMA_RXSTAT_CR | |
---|
625 | AU1X00_MAC_DMA_RXSTAT_DB | |
---|
626 | AU1X00_MAC_DMA_RXSTAT_RF)) == 0) { |
---|
627 | |
---|
628 | sc->rx_pkts++; |
---|
629 | |
---|
630 | /* find the start of the mbuf */ |
---|
631 | m = sc->rx_mbuf[sc->rx_head]; |
---|
632 | |
---|
633 | /* set the length of the mbuf */ |
---|
634 | m->m_len = AU1X00_MAC_DMA_RXSTAT_LEN(sc->rx_dma[sc->rx_head].stat); |
---|
635 | m->m_len -= 4; /* remove ethernet CRC */ |
---|
636 | |
---|
637 | m->m_pkthdr.len = m->m_len; |
---|
638 | |
---|
639 | /* strip off the ethernet header from the mbuf */ |
---|
640 | /* but save the pointer to it */ |
---|
641 | eh = mtod (m, struct ether_header *); |
---|
642 | m->m_data += sizeof(struct ether_header); |
---|
643 | |
---|
644 | /* give the received packet to the stack */ |
---|
645 | ether_input(ifp, eh, m); |
---|
646 | /* get a new buf and make it ready for the MAC */ |
---|
647 | MGETHDR(m, M_WAIT, MT_DATA); |
---|
648 | MCLGET(m, M_WAIT); |
---|
649 | |
---|
650 | m->m_pkthdr.rcvif = ifp; |
---|
651 | m->m_nextpkt = 0; |
---|
652 | |
---|
653 | /* |
---|
654 | * The receive buffer must be aligned with a cache line |
---|
655 | * boundary. |
---|
656 | */ |
---|
657 | { |
---|
658 | uint32_t *p = mtod(m, uint32_t *); |
---|
659 | *p = (mtod(m, uint32_t) + 0x1f) & ~0x1f; |
---|
660 | } |
---|
661 | |
---|
662 | } else { |
---|
663 | sc->rx_dropped++; |
---|
664 | |
---|
665 | /* find the mbuf so we can reuse it*/ |
---|
666 | m = sc->rx_mbuf[sc->rx_head]; |
---|
667 | } |
---|
668 | |
---|
669 | /* set up the receive dma to use the mbuf's cluster */ |
---|
670 | sc->rx_dma[sc->rx_head].addr = (mtod(m, uint32_t) & ~0xe0000000); |
---|
671 | au_sync(); |
---|
672 | sc->rx_mbuf[sc->rx_head] = m; |
---|
673 | |
---|
674 | sc->rx_dma[sc->rx_head].addr |= AU1X00_MAC_DMA_RXADDR_EN; |
---|
675 | au_sync(); |
---|
676 | |
---|
677 | |
---|
678 | /* increment the buffer index */ |
---|
679 | sc->rx_head++; |
---|
680 | if (sc->rx_head >= NUM_RX_DMA_BUFS) { |
---|
681 | sc->rx_head = 0; |
---|
682 | } |
---|
683 | } |
---|
684 | } |
---|
685 | } |
---|
686 | |
---|
687 | /* Send packet */ |
---|
688 | void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m) |
---|
689 | { |
---|
690 | struct mbuf *l = NULL; |
---|
691 | unsigned int pkt_offset = 0; |
---|
692 | au1x00_emac_softc_t *sc = (au1x00_emac_softc_t *)ifp->if_softc; |
---|
693 | uint32_t txbuf; |
---|
694 | |
---|
695 | /* Wait for EMAC Transmit Queue to become available. */ |
---|
696 | while((sc->tx_dma[sc->tx_head].addr & (AU1X00_MAC_DMA_TXADDR_EN || |
---|
697 | AU1X00_MAC_DMA_TXADDR_DN)) != 0) { |
---|
698 | continue; |
---|
699 | } |
---|
700 | |
---|
701 | /* copy the mbuf chain into the transmit buffer */ |
---|
702 | l = m; |
---|
703 | |
---|
704 | txbuf = (uint32_t)sc->tx_buf[sc->tx_head]; |
---|
705 | while (l != NULL) |
---|
706 | { |
---|
707 | |
---|
708 | memcpy(((char *)txbuf + pkt_offset), /* offset into pkt for mbuf */ |
---|
709 | (char *)mtod(l, void *), /* cast to void */ |
---|
710 | l->m_len); /* length of this mbuf */ |
---|
711 | |
---|
712 | pkt_offset += l->m_len; /* update offset */ |
---|
713 | l = l->m_next; /* get next mbuf, if any */ |
---|
714 | } |
---|
715 | |
---|
716 | /* Pad if necessary */ |
---|
717 | if (pkt_offset < 60) { |
---|
718 | memset((char *)(txbuf + pkt_offset), 0, (60 - pkt_offset)); |
---|
719 | pkt_offset = 60; |
---|
720 | } |
---|
721 | |
---|
722 | /* send it off */ |
---|
723 | sc->tx_dma[sc->tx_head].stat = 0; |
---|
724 | sc->tx_dma[sc->tx_head].len = pkt_offset; |
---|
725 | sc->tx_dma[sc->tx_head].addr = ((txbuf & ~0xe0000000) | |
---|
726 | AU1X00_MAC_DMA_TXADDR_EN); |
---|
727 | au_sync(); |
---|
728 | |
---|
729 | |
---|
730 | /* |
---|
731 | *Without this delay, some outgoing packets never |
---|
732 | * make it out the device. Nothing in the documentation |
---|
733 | * explains this. |
---|
734 | */ |
---|
735 | for (wait_count = 0; wait_count < 5000; wait_count++){ |
---|
736 | continue; |
---|
737 | } |
---|
738 | |
---|
739 | /* free the mbuf chain we just copied */ |
---|
740 | m_freem(m); |
---|
741 | |
---|
742 | sc->tx_head++; |
---|
743 | if (sc->tx_head >= NUM_TX_DMA_BUFS) { |
---|
744 | sc->tx_head = 0; |
---|
745 | } |
---|
746 | |
---|
747 | } /* au1x00_emac_sendpacket () */ |
---|
748 | |
---|
749 | |
---|
750 | |
---|
751 | /* Show interface statistics */ |
---|
752 | void au1x00_emac_stats (au1x00_emac_softc_t *sc) |
---|
753 | { |
---|
754 | printf("Interrupts:%-8lu", sc->interrupts); |
---|
755 | printf(" RX Interrupts:%-8lu", sc->rx_interrupts); |
---|
756 | printf(" TX Interrupts:%-8lu\n", sc->tx_interrupts); |
---|
757 | printf("RX Packets:%-8lu", sc->rx_pkts); |
---|
758 | printf(" RX Control:%-8lu", sc->rx_ctrl); |
---|
759 | printf(" RX broadcast:%-8lu\n", sc->rx_bcast); |
---|
760 | printf("RX Mcast:%-8lu", sc->rx_mcast); |
---|
761 | printf(" RX missed:%-8lu", sc->rx_missed); |
---|
762 | printf(" RX Unsupported ctrl:%-8lu\n", sc->rx_unsupp); |
---|
763 | printf("RX Len err:%-8lu", sc->rx_len_err); |
---|
764 | printf(" RX CRC err:%-8lu", sc->rx_crc_err); |
---|
765 | printf(" RX dribble:%-8lu\n", sc->rx_dribble); |
---|
766 | printf("RX MII err:%-8lu", sc->rx_mii_err); |
---|
767 | printf(" RX collision:%-8lu", sc->rx_collision); |
---|
768 | printf(" RX too long:%-8lu\n", sc->rx_too_long); |
---|
769 | printf("RX runt:%-8lu", sc->rx_runt); |
---|
770 | printf(" RX watchdog:%-8lu", sc->rx_watchdog); |
---|
771 | printf(" RX dropped:%-8lu\n", sc->rx_dropped); |
---|
772 | |
---|
773 | printf("TX Packets:%-8lu", sc->tx_pkts); |
---|
774 | printf(" TX Deferred:%-8lu", sc->tx_deferred); |
---|
775 | printf(" TX Underrun:%-8lu\n", sc->tx_underrun); |
---|
776 | printf("TX Aborted:%-8lu\n", sc->tx_aborted); |
---|
777 | |
---|
778 | } |
---|
779 | |
---|
780 | |
---|
781 | /* Driver ioctl handler */ |
---|
782 | static int |
---|
783 | au1x00_emac_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_t data) |
---|
784 | { |
---|
785 | au1x00_emac_softc_t *sc = ifp->if_softc; |
---|
786 | int error = 0; |
---|
787 | |
---|
788 | switch (command) { |
---|
789 | case SIOCGIFADDR: |
---|
790 | case SIOCSIFADDR: |
---|
791 | ether_ioctl (ifp, command, data); |
---|
792 | break; |
---|
793 | |
---|
794 | case SIOCSIFFLAGS: |
---|
795 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) |
---|
796 | { |
---|
797 | case IFF_RUNNING: |
---|
798 | au1x00_emac_stop (sc); |
---|
799 | break; |
---|
800 | |
---|
801 | case IFF_UP: |
---|
802 | au1x00_emac_init (sc); |
---|
803 | break; |
---|
804 | |
---|
805 | case IFF_UP | IFF_RUNNING: |
---|
806 | au1x00_emac_stop (sc); |
---|
807 | au1x00_emac_init (sc); |
---|
808 | break; |
---|
809 | |
---|
810 | default: |
---|
811 | break; |
---|
812 | } /* switch (if_flags) */ |
---|
813 | break; |
---|
814 | |
---|
815 | case SIO_RTEMS_SHOW_STATS: |
---|
816 | au1x00_emac_stats (sc); |
---|
817 | break; |
---|
818 | |
---|
819 | /* |
---|
820 | * FIXME: All sorts of multicast commands need to be added here! |
---|
821 | */ |
---|
822 | default: |
---|
823 | error = EINVAL; |
---|
824 | break; |
---|
825 | } /* switch (command) */ |
---|
826 | return error; |
---|
827 | } |
---|
828 | |
---|
829 | /* interrupt handler */ |
---|
830 | rtems_isr au1x00_emac_isr (rtems_vector_number v) |
---|
831 | { |
---|
832 | volatile au1x00_emac_softc_t *sc; |
---|
833 | int tx_flag = 0; |
---|
834 | int rx_flag = 0; |
---|
835 | |
---|
836 | sc = &softc[0]; |
---|
837 | if (v != AU1X00_IRQ_MAC0) { |
---|
838 | assert(v == AU1X00_IRQ_MAC0); |
---|
839 | } |
---|
840 | |
---|
841 | sc->interrupts++; |
---|
842 | |
---|
843 | /* |
---|
844 | * Since there's no easy way to find out the source of the |
---|
845 | * interrupt, we have to look at the tx and rx dma buffers |
---|
846 | */ |
---|
847 | /* receive interrupt */ |
---|
848 | while(sc->rx_dma[sc->rx_tail].addr & AU1X00_MAC_DMA_RXADDR_DN) { |
---|
849 | rx_flag = 1; |
---|
850 | sc->rx_interrupts++; |
---|
851 | sc->rx_dma[sc->rx_tail].addr &= ~AU1X00_MAC_DMA_RXADDR_DN; |
---|
852 | au_sync(); |
---|
853 | |
---|
854 | sc->rx_tail++; |
---|
855 | if (sc->rx_tail >= NUM_RX_DMA_BUFS) { |
---|
856 | sc->rx_tail = 0; |
---|
857 | } |
---|
858 | } |
---|
859 | if (rx_flag != 0) { |
---|
860 | rtems_event_send(sc->rx_daemon_tid, START_RX_EVENT); |
---|
861 | } |
---|
862 | |
---|
863 | /* transmit interrupt */ |
---|
864 | while (sc->tx_dma[sc->tx_tail].addr & AU1X00_MAC_DMA_TXADDR_DN) { |
---|
865 | uint32_t status; |
---|
866 | tx_flag = 1; |
---|
867 | sc->tx_interrupts++; |
---|
868 | |
---|
869 | status = sc->tx_dma[sc->tx_tail].stat; |
---|
870 | if (status & AU1X00_MAC_DMA_TXSTAT_DF) { |
---|
871 | sc->tx_deferred++; |
---|
872 | } |
---|
873 | if (status & AU1X00_MAC_DMA_TXSTAT_UR) { |
---|
874 | sc->tx_underrun++; |
---|
875 | } |
---|
876 | if (status & AU1X00_MAC_DMA_TXSTAT_FA) { |
---|
877 | sc->tx_aborted++; |
---|
878 | } |
---|
879 | |
---|
880 | sc->tx_dma[sc->tx_tail].addr = 0; |
---|
881 | au_sync(); |
---|
882 | |
---|
883 | sc->tx_tail++; |
---|
884 | if (sc->tx_tail >= NUM_TX_DMA_BUFS) { |
---|
885 | sc->tx_tail = 0; |
---|
886 | } |
---|
887 | } |
---|
888 | if (tx_flag != 0) { |
---|
889 | rtems_event_send(sc->tx_daemon_tid, START_TX_EVENT); |
---|
890 | } |
---|
891 | } |
---|
892 | |
---|