1 | /** |
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2 | * @file |
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3 | * |
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4 | * Au1x00 Interrupt Vectoring |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2005 by Cogent Computer Systems |
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9 | * Written by Jay Monkman <jtm@lopingdog.com> |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #include <rtems.h> |
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17 | #include <stdlib.h> |
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18 | #include <libcpu/au1x00.h> |
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19 | #include <libcpu/isr_entries.h> |
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20 | #include <rtems/irq.h> |
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21 | #include <bsp/irq.h> |
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22 | #include <bsp/irq-generic.h> |
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23 | |
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24 | static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *); |
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25 | |
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26 | #include <rtems/bspIo.h> /* for printk */ |
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27 | |
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28 | void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) |
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29 | { |
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30 | unsigned int sr; |
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31 | unsigned int cause; |
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32 | |
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33 | mips_get_sr( sr ); |
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34 | mips_get_cause( cause ); |
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35 | |
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36 | cause &= (sr & SR_IMASK); |
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37 | cause >>= CAUSE_IPSHIFT; |
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38 | |
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39 | /* count/compare interrupt */ |
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40 | if ( cause & 0x80 ) { |
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41 | unsigned long zero = 0; |
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42 | /* |
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43 | * I don't see a good way to disable the compare |
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44 | * interrupt, so let's just ignore it. |
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45 | */ |
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46 | __asm__ volatile ("mtc0 %0, $11\n" :: "r" (zero)); |
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47 | } |
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48 | |
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49 | /* Performance counter */ |
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50 | if ( cause & 0x40 ) { |
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51 | bsp_interrupt_handler_dispatch(AU1X00_IRQ_PERF); |
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52 | } |
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53 | |
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54 | /* Interrupt controller 0 */ |
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55 | if ( cause & 0x0c ) { |
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56 | call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR); |
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57 | } |
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58 | |
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59 | /* Interrupt controller 1 */ |
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60 | if ( cause & 0x30 ) { |
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61 | call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR); |
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62 | } |
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63 | |
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64 | /* SW[0] */ |
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65 | if ( cause & 0x01 ) |
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66 | bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW0 ); |
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67 | |
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68 | /* SW[1] */ |
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69 | if ( cause & 0x02 ) |
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70 | bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW1 ); |
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71 | } |
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72 | |
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73 | void mips_default_isr( int vector ) |
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74 | { |
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75 | unsigned int sr; |
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76 | unsigned int cause; |
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77 | |
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78 | mips_get_sr( sr ); |
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79 | mips_get_cause( cause ); |
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80 | |
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81 | printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", |
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82 | vector, cause, sr ); |
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83 | rtems_fatal_error_occurred(1); |
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84 | } |
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85 | |
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86 | static void call_vectored_isr( |
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87 | CPU_Interrupt_frame *frame, |
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88 | uint32_t cause, |
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89 | void *ctrlr |
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90 | ) |
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91 | { |
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92 | uint32_t src; |
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93 | uint32_t mask; |
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94 | int index; |
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95 | |
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96 | /* get mask register */ |
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97 | mask = AU1X00_IC_MASKRD(ctrlr); |
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98 | |
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99 | /* check request 0 */ |
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100 | src = AU1X00_IC_REQ0INT(ctrlr); |
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101 | src = src & mask; |
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102 | index = 0; |
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103 | while (src) { |
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104 | /* check LSB */ |
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105 | if (src & 1) { |
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106 | /* clear rising/falling edge detects */ |
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107 | AU1X00_IC_RISINGCLR(ctrlr) = (1 << index); |
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108 | AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index); |
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109 | au_sync(); |
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110 | bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index); |
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111 | } |
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112 | index ++; |
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113 | |
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114 | /* shift, and make sure MSB is clear */ |
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115 | src = (src >> 1) & 0x7fffffff; |
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116 | } |
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117 | |
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118 | /* check request 1 */ |
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119 | src = AU1X00_IC_REQ1INT(ctrlr); |
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120 | src = src & mask; |
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121 | index = 0; |
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122 | while (src) { |
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123 | /* check LSB */ |
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124 | if (src & 1) { |
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125 | /* clear rising/falling edge detects */ |
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126 | AU1X00_IC_RISINGCLR(ctrlr) = (1 << index); |
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127 | AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index); |
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128 | au_sync(); |
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129 | bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index); |
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130 | } |
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131 | index ++; |
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132 | |
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133 | /* shift, and make sure MSB is clear */ |
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134 | src = (src >> 1) & 0x7fffffff; |
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135 | } |
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136 | } |
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137 | |
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138 | /* Generate a software interrupt */ |
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139 | int assert_sw_irq(uint32_t irqnum) |
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140 | { |
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141 | uint32_t cause; |
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142 | |
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143 | if (irqnum <= 1) { |
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144 | mips_get_cause(cause); |
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145 | cause = cause | ((irqnum + 1) << CAUSE_IPSHIFT); |
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146 | mips_set_cause(cause); |
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147 | |
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148 | return irqnum; |
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149 | } else { |
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150 | return -1; |
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151 | } |
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152 | } |
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153 | |
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154 | /* Clear a software interrupt */ |
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155 | int negate_sw_irq(uint32_t irqnum) |
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156 | { |
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157 | uint32_t cause; |
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158 | |
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159 | if (irqnum <= 1) { |
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160 | mips_get_cause(cause); |
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161 | cause = cause & ~((irqnum + 1) << CAUSE_IPSHIFT); |
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162 | mips_set_cause(cause); |
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163 | |
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164 | return irqnum; |
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165 | } else { |
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166 | return -1; |
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167 | } |
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168 | } |
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