source: rtems/c/src/lib/libbsp/mips/csb350/include/tm27.h @ 6191ee4

4.104.114.84.95
Last change on this file since 6191ee4 was 7cde240, checked in by Jay Monkman <jtm@…>, on 02/25/05 at 05:18:07

2005-02-24 Jay Monkman <jtm@…>

  • acinclude.m4: Added csb350 to list of BSPs.
  • csb350/Makefile.am, csb350/README, csb350/bsp_specs, csb350/configure.ac, csb350/times, csb350/clock/clockdrv.c, csb350/console/console-io.c, csb350/include/bsp.h, csb350/include/tm27.h, csb350/network/network.c, csb350/start/regs.S, csb350/start/start.S, csb350/startup/bspclean.c, csb350/startup/bspstart.c, csb350/startup/linkcmds, csb350/timer/timer.c: New BSP.
  • Property mode set to 100644
File size: 1.7 KB
Line 
1/*
2 *  tm27.h
3 *
4 *  The license and distribution terms for this file may be
5 *  found in the file LICENSE in this distribution or at
6 *  http://www.rtems.com/license/LICENSE.
7 *
8 *  $Id$
9 */
10
11#ifndef _RTEMS_TMTEST27
12#error "This is an RTEMS internal file you must not include directly."
13#endif
14
15#ifndef __tm27_h
16#define __tm27_h
17
18/*
19 *  Define the interrupt mechanism for Time Test 27
20 */
21
22#define MUST_WAIT_FOR_INTERRUPT 1
23
24#if 0
25#define Install_tm27_vector( handler ) \
26    (void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \
27
28#define Cause_tm27_intr() \
29    asm volatile ( "syscall 0x01" : : );
30
31#define CLOCK_VECTOR TX3904_IRQ_TMR0
32
33#define Clear_tm27_intr() /* empty */
34
35#define Lower_tm27_intr() /* empty */
36#else
37#define Install_tm27_vector( handler ) \
38    (void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \
39
40#define Cause_tm27_intr() \
41  do { \
42    uint32_t   _clicks = 20; \
43    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
44    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
45    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
46    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
47    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xC0 ); \
48    *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
49  } while(0)
50
51#define Clear_tm27_intr() \
52  do { \
53    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
54    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
55    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR,   0x00 ); \
56  } while(0)
57
58#define Lower_tm27_intr() \
59  mips_enable_in_interrupt_mask( 0xff01 );
60
61#endif
62
63#endif
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