1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_interrupt |
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5 | * |
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6 | * @brief interrupt definitions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * COPYRIGHT (c) 1989-2012. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #ifndef LIBBSP_MIPS_AU1X00_IRQ_H |
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21 | #define LIBBSP_MIPS_AU1X00_IRQ_H |
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22 | |
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23 | #ifndef ASM |
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24 | #include <rtems.h> |
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25 | #include <rtems/irq.h> |
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26 | #include <rtems/irq-extension.h> |
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27 | #include <rtems/score/mips.h> |
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28 | #endif |
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29 | |
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30 | /** |
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31 | * @addtogroup bsp_interrupt |
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32 | * |
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33 | * @{ |
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34 | */ |
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35 | |
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36 | /* |
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37 | * Interrupt Vector Numbers |
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38 | * |
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39 | */ |
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40 | /* MIPS_INTERRUPT_BASE should be 32 (0x20) */ |
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41 | #define BSP_INTERRUPT_VECTOR_MIN 0 |
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42 | #define AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0) |
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43 | #define AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1) |
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44 | #define AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2) |
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45 | #define AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3) |
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46 | #define AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4) |
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47 | #define AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5) |
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48 | #define AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6) |
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49 | #define AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7) |
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50 | |
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51 | #define AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8) |
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52 | #define AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8) |
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53 | #define AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9) |
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54 | #define AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10) |
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55 | #define AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11) |
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56 | #define AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12) |
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57 | #define AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13) |
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58 | #define AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14) |
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59 | #define AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15) |
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60 | #define AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16) |
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61 | #define AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17) |
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62 | #define AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18) |
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63 | #define AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19) |
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64 | #define AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20) |
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65 | #define AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21) |
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66 | #define AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22) |
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67 | #define AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23) |
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68 | #define AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24) |
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69 | #define AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25) |
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70 | #define AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26) |
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71 | #define AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27) |
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72 | #define AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28) |
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73 | #define AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29) |
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74 | #define AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30) |
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75 | #define AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31) |
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76 | #define AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32) |
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77 | #define AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33) |
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78 | #define AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34) |
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79 | #define AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35) |
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80 | #define AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36) |
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81 | #define AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37) |
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82 | #define AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38) |
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83 | #define AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39) |
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84 | |
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85 | #define AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40) |
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86 | #define AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40) |
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87 | #define AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41) |
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88 | #define AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42) |
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89 | #define AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43) |
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90 | #define AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44) |
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91 | #define AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45) |
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92 | #define AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46) |
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93 | #define AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47) |
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94 | #define AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48) |
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95 | #define AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49) |
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96 | #define AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50) |
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97 | #define AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51) |
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98 | #define AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52) |
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99 | #define AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53) |
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100 | #define AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54) |
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101 | #define AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55) |
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102 | #define AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56) |
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103 | #define AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57) |
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104 | #define AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58) |
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105 | #define AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59) |
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106 | #define AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60) |
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107 | #define AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61) |
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108 | #define AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62) |
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109 | #define AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63) |
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110 | #define AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64) |
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111 | #define AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65) |
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112 | #define AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66) |
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113 | #define AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67) |
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114 | #define AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68) |
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115 | #define AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69) |
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116 | #define AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70) |
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117 | #define AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71) |
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118 | |
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119 | #define AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72) |
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120 | |
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121 | #define BSP_INTERRUPT_VECTOR_MAX AU1X00_MAXIMUM_VECTORS |
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122 | |
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123 | /** @} */ |
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124 | |
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125 | #endif /* LIBBSP_MIPS_AU1X00_IRQ_H */ |
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