[0c0181d] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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[7cde240] | 4 | * Instantiate the clock driver shell. |
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| 5 | * |
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[9927019a] | 6 | * This uses the TOY (Time of Year) timer to implement the clock. |
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[0c0181d] | 7 | */ |
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| 8 | |
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| 9 | /* |
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[7cde240] | 10 | * Copyright (c) 2005 by Cogent Computer Systems |
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| 11 | * Written by Jay Monkman <jtm@lopingdog.com> |
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[efdfd48] | 12 | * |
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[7cde240] | 13 | * The license and distribution terms for this file may be |
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[86f8ee90] | 14 | * found in the file LICENSE in this distribution or at |
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[c499856] | 15 | * http://www.rtems.org/license/LICENSE. |
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[7cde240] | 16 | */ |
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| 17 | |
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| 18 | #include <rtems.h> |
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| 19 | #include <bsp.h> |
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[0c0181d] | 20 | #include <bsp/irq.h> |
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[d3db8ae] | 21 | #include <rtems/bspIo.h> |
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[7cde240] | 22 | |
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[418899d] | 23 | uint32_t tick_interval; |
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| 24 | uint32_t last_match; |
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[7cde240] | 25 | |
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[0c0181d] | 26 | void au1x00_clock_init(void); |
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| 27 | |
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[7cde240] | 28 | #define CLOCK_VECTOR AU1X00_IRQ_TOY_MATCH2 |
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| 29 | |
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| 30 | #define Clock_driver_support_at_tick() \ |
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| 31 | do { \ |
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| 32 | while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0); \ |
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| 33 | last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR); \ |
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| 34 | AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + tick_interval; \ |
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| 35 | au_sync(); \ |
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| 36 | } while(0) |
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| 37 | |
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| 38 | /* Set for rising edge interrupt */ |
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| 39 | #define Clock_driver_support_install_isr( _new, _old ) \ |
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| 40 | do { \ |
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[0c0181d] | 41 | rtems_interrupt_handler_install( \ |
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| 42 | CLOCK_VECTOR, \ |
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| 43 | "clock", \ |
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| 44 | 0, \ |
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| 45 | _new, \ |
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| 46 | NULL \ |
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| 47 | ); \ |
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| 48 | AU1X00_IC_MASKCLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ |
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| 49 | AU1X00_IC_SRCSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ |
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| 50 | AU1X00_IC_CFG0SET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ |
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| 51 | AU1X00_IC_CFG1CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ |
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| 52 | AU1X00_IC_CFG2CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ |
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| 53 | AU1X00_IC_ASSIGNSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ |
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[7cde240] | 54 | } while(0) |
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| 55 | |
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| 56 | void au1x00_clock_init(void) |
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| 57 | { |
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[418899d] | 58 | uint32_t wakemask; |
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[efdfd48] | 59 | /* Clear the trim register */ |
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| 60 | AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0; |
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| 61 | |
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| 62 | /* Clear the TOY counter */ |
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| 63 | while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); |
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| 64 | AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0; |
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| 65 | while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); |
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| 66 | |
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| 67 | wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR); |
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[7cde240] | 68 | wakemask |= AU1X00_SYS_WAKEMSK_M20; |
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[efdfd48] | 69 | AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask; |
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[7cde240] | 70 | AU1X00_IC_WAKESET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; |
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[efdfd48] | 71 | |
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| 72 | tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick(); |
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| 73 | tick_interval = tick_interval / 1000000; |
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| 74 | |
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| 75 | last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR); |
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| 76 | AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval); |
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[7cde240] | 77 | AU1X00_IC_MASKSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; |
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[efdfd48] | 78 | while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0); |
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[7cde240] | 79 | } |
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| 80 | |
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| 81 | #define Clock_driver_support_initialize_hardware() \ |
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| 82 | do { \ |
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| 83 | au1x00_clock_init(); \ |
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| 84 | } while(0) |
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| 85 | |
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| 86 | #define Clock_driver_support_shutdown_hardware() |
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| 87 | |
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[75acd9e] | 88 | #define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER |
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| 89 | |
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[11978407] | 90 | #include "../../../shared/clockdrv_shell.h" |
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