1 | /* |
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2 | * BSP startup |
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3 | * |
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4 | * This routine starts the application. It includes application, |
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5 | * board, and monitor specific initialization and configuration. |
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6 | * The generic CPU dependent initialization has been performed |
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7 | * before this routine is invoked. |
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8 | * |
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9 | * Author: |
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10 | * David Fiddes, D.J@fiddes.surfaid.org |
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11 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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12 | * |
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13 | * COPYRIGHT (c) 1989-1998. |
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14 | * On-Line Applications Research Corporation (OAR). |
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15 | * Copyright assigned to U.S. Government, 1994. |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * |
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20 | * http://www.OARcorp.com/rtems/license.html. |
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21 | * |
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22 | * $Id$ |
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23 | */ |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <rtems/libio.h> |
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27 | #include <rtems/libcsupport.h> |
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28 | #include <string.h> |
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29 | #include <errno.h> |
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30 | |
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31 | /* |
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32 | * The original table from the application and our copy of it with |
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33 | * some changes. |
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34 | */ |
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35 | extern rtems_configuration_table Configuration; |
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36 | rtems_configuration_table BSP_Configuration; |
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37 | rtems_cpu_table Cpu_table; |
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38 | char *rtems_progname; |
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39 | |
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40 | /* |
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41 | * Location of 'VME' access |
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42 | */ |
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43 | #define VME_ONE_BASE 0x30000000 |
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44 | #define VME_TWO_BASE 0x31000000 |
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45 | |
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46 | /* |
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47 | * Cacheable areas |
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48 | */ |
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49 | #define SDRAM_BASE 0 |
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50 | #define SDRAM_SIZE (16*1024*1024) |
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51 | #define FLASH_BASE 0x10000000 |
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52 | #define FLASH_SIZE (4*1024*1024) |
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53 | |
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54 | /* |
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55 | * CPU-space access |
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56 | */ |
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57 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) |
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58 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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59 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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60 | |
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61 | /* |
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62 | * Read/write copy of common cache |
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63 | * Split I/D cache |
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64 | * Allow CPUSHL to invalidate a cache line |
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65 | * Enable buffered writes |
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66 | * No burst transfers on non-cacheable accesses |
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67 | * Default cache mode is *disabled* (cache only ACRx areas) |
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68 | */ |
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69 | static uint32_t cacr_mode = MCF5XXX_CACR_CENB | |
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70 | MCF5XXX_CACR_DBWE | |
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71 | MCF5XXX_CACR_DCM; |
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72 | /* |
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73 | * Cannot be frozen |
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74 | */ |
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75 | void _CPU_cache_freeze_data(void) {} |
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76 | void _CPU_cache_unfreeze_data(void) {} |
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77 | void _CPU_cache_freeze_instruction(void) {} |
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78 | void _CPU_cache_unfreeze_instruction(void) {} |
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79 | |
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80 | /* |
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81 | * Write-through data cache -- flushes are unnecessary |
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82 | */ |
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83 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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84 | void _CPU_cache_flush_entire_data(void) {} |
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85 | |
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86 | void _CPU_cache_enable_instruction(void) |
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87 | { |
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88 | rtems_interrupt_level level; |
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89 | |
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90 | rtems_interrupt_disable(level); |
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91 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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92 | m68k_set_cacr(cacr_mode); |
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93 | rtems_interrupt_enable(level); |
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94 | } |
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95 | |
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96 | void _CPU_cache_disable_instruction(void) |
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97 | { |
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98 | rtems_interrupt_level level; |
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99 | |
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100 | rtems_interrupt_disable(level); |
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101 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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102 | m68k_set_cacr(cacr_mode); |
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103 | rtems_interrupt_enable(level); |
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104 | } |
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105 | |
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106 | void _CPU_cache_invalidate_entire_instruction(void) |
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107 | { |
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108 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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109 | } |
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110 | |
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111 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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112 | { |
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113 | /* |
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114 | * Top half of cache is I-space |
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115 | */ |
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116 | addr = (void *)((int)addr | 0x400); |
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117 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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118 | } |
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119 | |
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120 | void _CPU_cache_enable_data(void) |
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121 | { |
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122 | rtems_interrupt_level level; |
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123 | |
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124 | rtems_interrupt_disable(level); |
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125 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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126 | m68k_set_cacr(cacr_mode); |
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127 | rtems_interrupt_enable(level); |
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128 | } |
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129 | |
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130 | void _CPU_cache_disable_data(void) |
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131 | { |
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132 | rtems_interrupt_level level; |
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133 | |
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134 | rtems_interrupt_disable(level); |
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135 | rtems_interrupt_disable(level); |
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136 | cacr_mode |= MCF5XXX_CACR_DISD; |
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137 | m68k_set_cacr(cacr_mode); |
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138 | rtems_interrupt_enable(level); |
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139 | } |
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140 | |
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141 | void _CPU_cache_invalidate_entire_data(void) |
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142 | { |
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143 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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144 | } |
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145 | |
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146 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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147 | { |
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148 | /* |
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149 | * Bottom half of cache is D-space |
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150 | */ |
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151 | addr = (void *)((int)addr & ~0x400); |
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152 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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153 | } |
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154 | |
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155 | /* |
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156 | * Use the shared implementations of the following routines |
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157 | */ |
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158 | void bsp_postdriver_hook(void); |
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159 | void bsp_libc_init( void *, uint32_t, int ); |
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160 | void bsp_pretasking_hook(void); /* m68k version */ |
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161 | |
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162 | /* |
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163 | * bsp_start |
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164 | * |
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165 | * This routine does the bulk of the system initialisation. |
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166 | */ |
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167 | void bsp_start( void ) |
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168 | { |
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169 | extern char _WorkspaceBase[]; |
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170 | extern char _RamSize[]; |
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171 | extern unsigned long _M68k_Ramsize; |
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172 | |
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173 | _M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */ |
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174 | |
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175 | /* |
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176 | * Allocate the memory for the RTEMS Work Space. This can come from |
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177 | * a variety of places: hard coded address, malloc'ed from outside |
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178 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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179 | * typically done by stock BSPs) by subtracting the required amount |
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180 | * of work space from the last physical address on the CPU board. |
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181 | */ |
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182 | |
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183 | /* |
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184 | * Need to "allocate" the memory for the RTEMS Workspace and |
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185 | * tell the RTEMS configuration where it is. This memory is |
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186 | * not malloc'ed. It is just "pulled from the air". |
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187 | */ |
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188 | |
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189 | BSP_Configuration.work_space_start = (void *)_WorkspaceBase; |
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190 | |
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191 | /* |
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192 | * initialize the CPU table for this BSP |
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193 | */ |
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194 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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195 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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196 | Cpu_table.do_zero_of_workspace = TRUE; |
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197 | Cpu_table.interrupt_stack_size = 4096; |
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198 | |
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199 | Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */ |
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200 | |
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201 | /* |
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202 | * Invalidate the cache and disable it |
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203 | */ |
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204 | m68k_set_acr0(0); |
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205 | m68k_set_acr1(0); |
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206 | m68k_set_cacr(MCF5XXX_CACR_CINV); |
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207 | |
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208 | /* |
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209 | * Cache SDRAM and FLASH |
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210 | */ |
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211 | m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE) | |
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212 | MCF5XXX_ACR_AM(SDRAM_SIZE-1) | |
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213 | MCF5XXX_ACR_EN | |
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214 | MCF5XXX_ACR_BWE | |
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215 | MCF5XXX_ACR_SM_IGNORE); |
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216 | m68k_set_acr1(MCF5XXX_ACR_AB(FLASH_BASE) | |
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217 | MCF5XXX_ACR_AM(FLASH_SIZE-1) | |
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218 | MCF5XXX_ACR_EN | |
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219 | MCF5XXX_ACR_BWE | |
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220 | MCF5XXX_ACR_SM_IGNORE); |
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221 | |
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222 | /* |
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223 | * Enable the cache |
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224 | */ |
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225 | m68k_set_cacr(cacr_mode); |
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226 | |
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227 | /* |
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228 | * Set up CS* space (fake 'VME') |
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229 | * Two A24/D16 spaces, supervisor data acces |
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230 | */ |
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231 | MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE); |
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232 | MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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233 | MCF5282_CS_CSMR_CI | |
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234 | MCF5282_CS_CSMR_SC | |
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235 | MCF5282_CS_CSMR_UC | |
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236 | MCF5282_CS_CSMR_UD | |
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237 | MCF5282_CS_CSMR_V; |
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238 | MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16; |
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239 | MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE); |
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240 | MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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241 | MCF5282_CS_CSMR_CI | |
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242 | MCF5282_CS_CSMR_SC | |
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243 | MCF5282_CS_CSMR_UC | |
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244 | MCF5282_CS_CSMR_UD | |
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245 | MCF5282_CS_CSMR_V; |
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246 | MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16; |
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247 | } |
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248 | |
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249 | uint32_t bsp_get_CPU_clock_speed(void) |
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250 | { |
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251 | extern char _CPUClockSpeed[]; |
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252 | return( (uint32_t)_CPUClockSpeed); |
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253 | } |
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254 | |
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255 | /* |
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256 | * Interrupt controller allocation |
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257 | */ |
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258 | rtems_status_code |
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259 | bsp_allocate_interrupt(int level, int priority) |
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260 | { |
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261 | static char used[7]; |
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262 | rtems_interrupt_level l; |
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263 | rtems_status_code ret = RTEMS_RESOURCE_IN_USE; |
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264 | |
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265 | if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) |
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266 | return RTEMS_INVALID_NUMBER; |
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267 | rtems_interrupt_disable(l); |
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268 | if ((used[level-1] & (1 << priority)) == 0) { |
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269 | used[level-1] |= (1 << priority); |
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270 | ret = RTEMS_SUCCESSFUL; |
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271 | } |
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272 | rtems_interrupt_enable(l); |
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273 | return ret; |
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274 | } |
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275 | |
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276 | /* |
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277 | * Arcturus bootloader system calls |
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278 | */ |
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279 | #define syscall_return(type, ret) \ |
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280 | do { \ |
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281 | if ((unsigned long)(ret) >= (unsigned long)(-64)) { \ |
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282 | errno = -(ret); \ |
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283 | ret = -1; \ |
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284 | } \ |
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285 | return (type)(ret); \ |
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286 | } while (0) |
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287 | #define syscall_1(type,name,d1type,d1) \ |
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288 | type uC5282_##name(d1type d1) \ |
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289 | { \ |
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290 | long ret; \ |
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291 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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292 | __asm__ __volatile__ ("move.l %0,%%d0\n\t" \ |
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293 | "trap #2\n\t" \ |
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294 | "move.l %%d0,%0" \ |
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295 | : "=g" (ret) \ |
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296 | : "d" (SysCode_##name), "d" (__d1) \ |
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297 | : "d0" ); \ |
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298 | syscall_return(type,ret); \ |
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299 | } |
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300 | #define SysCode_gethwaddr 12 /* get hardware address */ |
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301 | #define SysCode_getbenv 14 /* get bootloader environment variable */ |
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302 | #define SysCode_setbenv 15 /* get bootloader environment variable */ |
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303 | syscall_1(unsigned const char *, gethwaddr, int, a) |
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304 | syscall_1(const char *, getbenv, const char *, a) |
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305 | |
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306 | |
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307 | /* |
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308 | * 'Extended BSP' routines |
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309 | * Should move to cpukit/score/cpu/m68k/cpu.c someday. |
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310 | */ |
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311 | |
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312 | rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; } |
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313 | int BSP_enableVME_int_lvl(unsigned int level) { return 0; } |
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314 | int BSP_disableVME_int_lvl(unsigned int level) { return 0; } |
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315 | |
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316 | /* |
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317 | * VME interrupt support |
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318 | */ |
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319 | #define NVECTOR 256 |
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320 | |
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321 | static struct handlerTab { |
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322 | BSP_VME_ISR_t func; |
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323 | void *arg; |
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324 | } handlerTab[NVECTOR]; |
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325 | |
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326 | BSP_VME_ISR_t |
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327 | BSP_getVME_isr(unsigned long vector, void **pusrArg) |
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328 | { |
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329 | if (vector >= NVECTOR) |
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330 | return (BSP_VME_ISR_t)NULL; |
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331 | if (pusrArg) |
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332 | *pusrArg = handlerTab[vector].arg; |
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333 | return handlerTab[vector].func; |
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334 | } |
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335 | |
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336 | static rtems_isr |
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337 | trampoline (rtems_vector_number v) |
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338 | { |
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339 | if (handlerTab[v].func) |
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340 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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341 | } |
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342 | |
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343 | int |
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344 | BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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345 | { |
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346 | rtems_isr_entry old_handler; |
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347 | |
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348 | if (vector >= NVECTOR) |
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349 | return -1; |
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350 | handlerTab[vector].func = handler; |
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351 | handlerTab[vector].arg = usrArg; |
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352 | rtems_interrupt_catch(trampoline, vector, &old_handler); |
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353 | |
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354 | /* |
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355 | * Find an unused level/priority if this is an on-chip (INTC0) |
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356 | * source and this is the first time the source is being used. |
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357 | * Interrupt sources 1 through 7 are fixed level/priority |
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358 | */ |
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359 | if ((vector >= 65) && (vector <= 127)) { |
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360 | int l, p; |
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361 | int source = vector - 64; |
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362 | rtems_interrupt_level level; |
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363 | static unsigned char installed[8]; |
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364 | |
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365 | if (installed[source/8] & (1 << (source % 8))) |
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366 | return 0; |
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367 | installed[source/8] |= (1 << (source % 8)); |
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368 | for (l = 1 ; l < 7 ; l++) { |
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369 | for (p = 0 ; p < 7 ; p++) { |
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370 | if ((source < 8) |
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371 | || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) { |
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372 | if (source < 8) |
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373 | *(&MCF5282_INTC0_ICR1 + (source - 1)) = |
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374 | MCF5282_INTC_ICR_IL(l) | |
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375 | MCF5282_INTC_ICR_IP(p); |
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376 | rtems_interrupt_disable(level); |
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377 | if (source >= 32) |
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378 | MCF5282_INTC0_IMRH &= ~(1 << (source - 32)); |
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379 | else |
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380 | MCF5282_INTC0_IMRL &= ~((1 << source) | |
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381 | MCF5282_INTC_IMRL_MASKALL); |
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382 | rtems_interrupt_enable(level); |
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383 | return 0; |
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384 | } |
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385 | } |
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386 | } |
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387 | return -1; |
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388 | } |
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389 | return 0; |
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390 | } |
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391 | |
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392 | int |
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393 | BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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394 | { |
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395 | if (vector >= NVECTOR) |
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396 | return -1; |
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397 | if ((handlerTab[vector].func != handler) |
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398 | || (handlerTab[vector].arg != usrArg)) |
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399 | return -1; |
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400 | handlerTab[vector].func = (BSP_VME_ISR_t)NULL; |
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401 | return 0; |
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402 | } |
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403 | |
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404 | int |
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405 | BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr) |
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406 | { |
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407 | unsigned long offset; |
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408 | |
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409 | switch (am) { |
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410 | default: return -1; |
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411 | case VME_AM_SUP_SHORT_IO: offset = 0x31000000; break; /* A16/D16 */ |
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412 | case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */ |
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413 | case VME_AM_EXT_SUP_DATA: return -1; /* A32/D32 */ |
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414 | } |
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415 | *plocaladdr = vmeaddr + offset; |
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416 | return 0; |
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417 | } |
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