source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ d5fe91e

4.104.114.84.95
Last change on this file since d5fe91e was d5fe91e, checked in by Eric Norum <WENorum@…>, on Apr 19, 2005 at 8:50:45 PM

Expose some read/write copies of configuration registers.

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File size: 17.8 KB
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1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
29#include <errno.h>
30 
31/*
32 *  The original table from the application and our copy of it with
33 *  some changes.
34 */
35extern rtems_configuration_table Configuration;
36rtems_configuration_table  BSP_Configuration;
37rtems_cpu_table Cpu_table;
38char *rtems_progname;
39
40/*
41 * Location of 'VME' access
42 */
43#define VME_ONE_BASE    0x30000000
44#define VME_TWO_BASE    0x31000000
45
46/*
47 * CPU-space access
48 * The NOP after writing the CACR is there to address the following issue as
49 * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
50 *
51 * 6 Possible Cache Corruption after Setting  CACR[CINV]
52 * 6.1 Description
53 * The cache on the MCF5282 was enhanced to function as a unified data and
54 * instruction cache, an instruction cache, or an operand cache.  The cache
55 * function and organization is controlled by the cache control register (CACR).
56 * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
57 * If the cache is configured as a unified cache and the CINV bit is set, the
58 * scope of the cache clear is controlled by two other bits in the CACR,
59 * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
60 * cache only).  These bits allow the entire cache, just the instruction
61 * portion of the cache, or just the data portion of the cache to be cleared.
62 * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
63 * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
64 * then cache corruption may  occur.
65 *
66 * 6.2 Workaround
67 * All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
68 * should be followed immediately by a NOP instruction.  This avoids the cache
69 * corruption problem.
70 * DATECODES AFFECTED: All
71 */
72#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr))
73#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
74#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
75
76/*
77 * Read/write copy of cache registers
78 *   Split I/D cache
79 *   Allow CPUSHL to invalidate a cache line
80 *   Enable buffered writes
81 *   No burst transfers on non-cacheable accesses
82 *   Default cache mode is *disabled* (cache only ACRx areas)
83 */
84uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
85                             MCF5XXX_CACR_DBWE |
86                             MCF5XXX_CACR_DCM;
87uint32_t mcf5282_acr0_mode = 0;
88uint32_t mcf5282_acr1_mode = 0;
89/*
90 * Cannot be frozen
91 */
92void _CPU_cache_freeze_data(void) {}
93void _CPU_cache_unfreeze_data(void) {}
94void _CPU_cache_freeze_instruction(void) {}
95void _CPU_cache_unfreeze_instruction(void) {}
96
97/*
98 * Write-through data cache -- flushes are unnecessary
99 */
100void _CPU_cache_flush_1_data_line(const void *d_addr) {}
101void _CPU_cache_flush_entire_data(void) {}
102
103void _CPU_cache_enable_instruction(void)
104{
105    rtems_interrupt_level level;
106
107    rtems_interrupt_disable(level);
108    mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
109    m68k_set_cacr(mcf5282_cacr_mode);
110    rtems_interrupt_enable(level);
111}
112
113void _CPU_cache_disable_instruction(void)
114{
115    rtems_interrupt_level level;
116
117    rtems_interrupt_disable(level);
118    mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI;
119    m68k_set_cacr(mcf5282_cacr_mode);
120    rtems_interrupt_enable(level);
121}
122
123void _CPU_cache_invalidate_entire_instruction(void)
124{
125    m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
126}
127
128void _CPU_cache_invalidate_1_instruction_line(const void *addr)
129{
130    /*
131     * Top half of cache is I-space
132     */
133    addr = (void *)((int)addr | 0x400);
134    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
135}
136
137void _CPU_cache_enable_data(void)
138{
139    rtems_interrupt_level level;
140
141    rtems_interrupt_disable(level);
142    mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD;
143    m68k_set_cacr(mcf5282_cacr_mode);
144    rtems_interrupt_enable(level);
145}
146
147void _CPU_cache_disable_data(void)
148{
149    rtems_interrupt_level level;
150
151    rtems_interrupt_disable(level);
152    rtems_interrupt_disable(level);
153    mcf5282_cacr_mode |= MCF5XXX_CACR_DISD;
154    m68k_set_cacr(mcf5282_cacr_mode);
155    rtems_interrupt_enable(level);
156}
157
158void _CPU_cache_invalidate_entire_data(void)
159{
160    m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
161}
162
163void _CPU_cache_invalidate_1_data_line(const void *addr)
164{
165    /*
166     * Bottom half of cache is D-space
167     */
168    addr = (void *)((int)addr & ~0x400);
169    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
170}
171
172/*
173 *  Use the shared implementations of the following routines
174 */
175void bsp_postdriver_hook(void);
176void bsp_libc_init( void *, uint32_t, int );
177void bsp_pretasking_hook(void);         /* m68k version */
178
179/*
180 *  bsp_start
181 *
182 *  This routine does the bulk of the system initialisation.
183 */
184void bsp_start( void )
185{
186  extern char _WorkspaceBase[];
187  extern char _RamBase[], _RamSize[];
188  extern unsigned long  _M68k_Ramsize;
189
190  _M68k_Ramsize = (unsigned long)_RamSize;      /* RAM size set in linker script */
191
192  /*
193   *  Allocate the memory for the RTEMS Work Space.  This can come from
194   *  a variety of places: hard coded address, malloc'ed from outside
195   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
196   *  typically done by stock BSPs) by subtracting the required amount
197   *  of work space from the last physical address on the CPU board.
198   */
199
200  /*
201   *  Need to "allocate" the memory for the RTEMS Workspace and
202   *  tell the RTEMS configuration where it is.  This memory is
203   *  not malloc'ed.  It is just "pulled from the air".
204   */
205
206  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
207
208  /*
209   *  initialize the CPU table for this BSP
210   */
211  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
212  Cpu_table.postdriver_hook = bsp_postdriver_hook;
213  Cpu_table.do_zero_of_workspace = TRUE;
214  Cpu_table.interrupt_stack_size = 4096;
215
216  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
217
218    /*
219     * Invalidate the cache and disable it
220     */
221    m68k_set_acr0(mcf5282_acr0_mode);
222    m68k_set_acr1(mcf5282_acr1_mode);
223    m68k_set_cacr(MCF5XXX_CACR_CINV);
224
225    /*
226     * Cache SDRAM
227     */
228    mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
229                        MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
230                        MCF5XXX_ACR_EN                         |
231                        MCF5XXX_ACR_BWE                        |
232                        MCF5XXX_ACR_SM_IGNORE;
233    m68k_set_acr0(mcf5282_acr0_mode);
234
235    /*
236     * Enable the cache
237     */
238    m68k_set_cacr(mcf5282_cacr_mode);
239
240    /*
241     * Set up CS* space (fake 'VME')
242     *   Two A24/D16 spaces, supervisor data acces
243     */
244    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
245    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | 
246                       MCF5282_CS_CSMR_CI |
247                       MCF5282_CS_CSMR_SC |
248                       MCF5282_CS_CSMR_UC |
249                       MCF5282_CS_CSMR_UD |
250                       MCF5282_CS_CSMR_V;
251    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
252    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
253    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | 
254                       MCF5282_CS_CSMR_CI |
255                       MCF5282_CS_CSMR_SC |
256                       MCF5282_CS_CSMR_UC |
257                       MCF5282_CS_CSMR_UD |
258                       MCF5282_CS_CSMR_V;
259    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
260}
261
262uint32_t bsp_get_CPU_clock_speed(void)
263{
264    extern char _CPUClockSpeed[];
265    return( (uint32_t)_CPUClockSpeed);
266}
267
268/*
269 * Interrupt controller allocation
270 */
271rtems_status_code
272bsp_allocate_interrupt(int level, int priority)
273{
274    static char used[7];
275    rtems_interrupt_level l;
276    rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
277
278    if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
279        return RTEMS_INVALID_NUMBER;
280    rtems_interrupt_disable(l);
281    if ((used[level-1] & (1 << priority)) == 0) {
282        used[level-1] |= (1 << priority);
283        ret = RTEMS_SUCCESSFUL;
284    }
285    rtems_interrupt_enable(l);
286    return ret;
287}
288
289/*
290 * Arcturus bootloader system calls
291 */
292#define syscall_return(type, ret)                      \
293do {                                                   \
294   if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
295      errno = -(ret);                                  \
296      ret = -1;                                        \
297   }                                                   \
298   return (type)(ret);                                 \
299} while (0)
300#define syscall_1(type,name,d1type,d1)                      \
301type bsp_##name(d1type d1)                                  \
302{                                                           \
303   long ret;                                                \
304   register long __d1 __asm__ ("%d1") = (long)d1;           \
305   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
306                         "trap #2\n\t"                      \
307                         "move.l %%d0,%0"                   \
308                         : "=g" (ret)                       \
309                         : "i" (SysCode_##name), "d" (__d1) \
310                         : "d0" );                          \
311   syscall_return(type,ret);                                \
312}
313#define syscall_2(type,name,d1type,d1,d2type,d2)            \
314type bsp_##name(d1type d1, d2type d2)                       \
315{                                                           \
316   long ret;                                                \
317   register long __d1 __asm__ ("%d1") = (long)d1;           \
318   register long __d2 __asm__ ("%d2") = (long)d2;           \
319   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
320                         "trap #2\n\t"                      \
321                         "move.l %%d0,%0"                   \
322                         : "=g" (ret)                       \
323                         : "i" (SysCode_##name), "d" (__d1),\
324                                                 "d" (__d2) \
325                         : "d0" );                          \
326   syscall_return(type,ret);                                \
327}
328#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3)  \
329type bsp_##name(d1type d1, d2type d2, d3type d3)            \
330{                                                           \
331   long ret;                                                \
332   register long __d1 __asm__ ("%d1") = (long)d1;           \
333   register long __d2 __asm__ ("%d2") = (long)d2;           \
334   register long __d3 __asm__ ("%d3") = (long)d3;           \
335   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
336                         "trap #2\n\t"                      \
337                         "move.l %%d0,%0"                   \
338                         : "=g" (ret)                       \
339                         : "i" (SysCode_##name), "d" (__d1),\
340                                                 "d" (__d2),\
341                                                 "d" (__d3) \
342                         : "d0" );                          \
343   syscall_return(type,ret);                                \
344}
345#define SysCode_reset              0 /* reset */
346#define SysCode_program            5 /* program flash memory */
347#define SysCode_gethwaddr         12 /* get hardware address */
348#define SysCode_getbenv           14 /* get bootloader environment variable */
349#define SysCode_setbenv           15 /* get bootloader environment variable */
350#define SysCode_flash_erase_range 19 /* erase a section of flash */
351#define SysCode_flash_write_range 20 /* write a section of flash */
352syscall_1(unsigned const char *, gethwaddr, int, a)
353syscall_1(const char *, getbenv, const char *, a)
354syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
355syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
356syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
357
358/*
359 * 'Extended BSP' routines
360 * Should move to cpukit/score/cpu/m68k/cpu.c someday.
361 */
362
363rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
364int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
365int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
366
367/*
368 * 'VME' interrupt support
369 * Interrupt vectors 192-255 are set aside for use by external logic which
370 * drives IRQ1*.  The actual interrupt source is read from the external
371 * logic at FPGA_IRQ_INFO.  The most-significant bit of the least-significant
372 * byte read from this location is set as long as the external logic has
373 * interrupts to be serviced.  The least-significant six bits indicate the
374 * interrupt source within the external logic and are used to select the
375 * specified interupt handler.
376 */
377#define NVECTOR 256
378#define FPGA_VECTOR (64+1)  /* IRQ1* pin connected to external FPGA */
379#define FPGA_EPPAR  MCF5282_EPORT_EPPAR_EPPA1_LEVEL
380#define FPGA_EPDDR  MCF5282_EPORT_EPDDR_EPDD1
381#define FPGA_EPIER  MCF5282_EPORT_EPIER_EPIE1
382#define FPGA_EPPDR  MCF5282_EPORT_EPPDR_EPPD1
383#define FPGA_IRQ_INFO    *((vuint16 *)(0x31000000 + 0xfffffe))
384
385static struct handlerTab {
386    BSP_VME_ISR_t func;
387    void         *arg;
388} handlerTab[NVECTOR];
389
390BSP_VME_ISR_t
391BSP_getVME_isr(unsigned long vector, void **pusrArg)
392{
393    if (vector >= NVECTOR)
394        return (BSP_VME_ISR_t)NULL;
395    if (pusrArg)
396        *pusrArg = handlerTab[vector].arg;
397    return handlerTab[vector].func;
398}
399
400static rtems_isr
401trampoline (rtems_vector_number v)
402{
403    /*
404     * Handle FPGA interrupts until all have been consumed
405     */
406    if (v == FPGA_VECTOR) {
407        while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
408            v = 192 + (v & 0x3f);
409            if (handlerTab[v].func) 
410                (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
411            else
412                rtems_fatal_error_occurred(v);
413        }
414    }
415    else if (handlerTab[v].func) 
416        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
417}
418
419int
420BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
421{
422    rtems_isr_entry old_handler;
423    rtems_interrupt_level level;
424
425    /*
426     * Register the handler information
427     */
428    if (vector >= NVECTOR)
429        return -1;
430    handlerTab[vector].func = handler;
431    handlerTab[vector].arg = usrArg;
432
433    /*
434     * If this is an external FPGA ('VME') vector set up the real IRQ.
435     */
436    if ((vector >= 192) && (vector <= 255)) {
437        int i;
438        static volatile int setupDone;
439        rtems_interrupt_disable(level);
440        if (setupDone) {
441            rtems_interrupt_enable(level);
442            return 0;
443        }
444        MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
445        MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
446        MCF5282_EPORT_EPIER |=  FPGA_EPIER;
447        MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
448                                MCF5282_INTC_IMRL_MASKALL);
449        setupDone = 1;
450        i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL);
451        rtems_interrupt_enable(level);
452        return i;
453    }
454
455    /*
456     * Make the connection between the interrupt and the local handler
457     */
458    rtems_interrupt_catch(trampoline, vector, &old_handler);
459
460    /*
461     * Find an unused level/priority if this is an on-chip (INTC0)
462     * source and this is the first time the source is being used.
463     * Interrupt sources 1 through 7 are fixed level/priority
464     */
465    if ((vector >= 65) && (vector <= 127)) {
466        int l, p;
467        int source = vector - 64;
468        static unsigned char installed[8];
469
470        rtems_interrupt_disable(level);
471        if (installed[source/8] & (1 << (source % 8))) {
472            rtems_interrupt_enable(level);
473            return 0;
474        }
475        installed[source/8] |= (1 << (source % 8));
476        rtems_interrupt_enable(level);
477        for (l = 1 ; l < 7 ; l++) {
478            for (p = 0 ; p < 8 ; p++) {
479                if ((source < 8)
480                 || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
481                    if (source >= 8)
482                        *(&MCF5282_INTC0_ICR1 + (source - 1)) = 
483                                                       MCF5282_INTC_ICR_IL(l) |
484                                                       MCF5282_INTC_ICR_IP(p);
485                    rtems_interrupt_disable(level);
486                    if (source >= 32)
487                        MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
488                    else
489                        MCF5282_INTC0_IMRL &= ~((1 << source) |
490                                                MCF5282_INTC_IMRL_MASKALL);
491                    rtems_interrupt_enable(level);
492                    return 0;
493                }
494            }
495        }
496        return -1;
497    }
498    return 0;
499}
500
501int
502BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
503{
504    if (vector >= NVECTOR)
505        return -1;
506    if ((handlerTab[vector].func != handler)
507     || (handlerTab[vector].arg != usrArg))
508        return -1;
509    handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
510    return 0;
511}
512
513int
514BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
515{
516    unsigned long offset;
517
518    switch (am) {
519    default:    return -1;
520    case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
521    case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
522    case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
523    }
524    *plocaladdr = vmeaddr + offset;
525    return 0;
526}
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