1 | /* |
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2 | * BSP startup |
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3 | * |
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4 | * This routine starts the application. It includes application, |
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5 | * board, and monitor specific initialization and configuration. |
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6 | * The generic CPU dependent initialization has been performed |
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7 | * before this routine is invoked. |
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8 | * |
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9 | * Author: |
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10 | * David Fiddes, D.J@fiddes.surfaid.org |
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11 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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12 | * |
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13 | * COPYRIGHT (c) 1989-1998. |
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14 | * On-Line Applications Research Corporation (OAR). |
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15 | * Copyright assigned to U.S. Government, 1994. |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * |
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20 | * http://www.OARcorp.com/rtems/license.html. |
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21 | * |
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22 | * $Id$ |
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23 | */ |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <rtems/libio.h> |
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27 | #include <rtems/libcsupport.h> |
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28 | #include <string.h> |
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29 | #include <errno.h> |
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30 | |
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31 | /* |
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32 | * The original table from the application and our copy of it with |
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33 | * some changes. |
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34 | */ |
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35 | extern rtems_configuration_table Configuration; |
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36 | rtems_configuration_table BSP_Configuration; |
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37 | rtems_cpu_table Cpu_table; |
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38 | char *rtems_progname; |
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39 | |
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40 | /* |
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41 | * Location of 'VME' access |
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42 | */ |
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43 | #define VME_ONE_BASE 0x30000000 |
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44 | #define VME_TWO_BASE 0x31000000 |
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45 | |
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46 | /* |
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47 | * CPU-space access |
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48 | * The NOP after writing the CACR is there to address the following issue as |
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49 | * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004: |
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50 | * |
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51 | * 6 Possible Cache Corruption after Setting CACR[CINV] |
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52 | * 6.1 Description |
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53 | * The cache on the MCF5282 was enhanced to function as a unified data and |
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54 | * instruction cache, an instruction cache, or an operand cache. The cache |
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55 | * function and organization is controlled by the cache control register (CACR). |
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56 | * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear. |
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57 | * If the cache is configured as a unified cache and the CINV bit is set, the |
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58 | * scope of the cache clear is controlled by two other bits in the CACR, |
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59 | * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data |
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60 | * cache only). These bits allow the entire cache, just the instruction |
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61 | * portion of the cache, or just the data portion of the cache to be cleared. |
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62 | * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set) |
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63 | * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set), |
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64 | * then cache corruption may occur. |
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65 | * |
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66 | * 6.2 Workaround |
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67 | * All loads of the CACR that perform a cache clear operation (CINV = BIT 24) |
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68 | * should be followed immediately by a NOP instruction. This avoids the cache |
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69 | * corruption problem. |
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70 | * DATECODES AFFECTED: All |
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71 | */ |
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72 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr)) |
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73 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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74 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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75 | |
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76 | /* |
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77 | * Read/write copy of common cache |
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78 | * Split I/D cache |
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79 | * Allow CPUSHL to invalidate a cache line |
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80 | * Enable buffered writes |
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81 | * No burst transfers on non-cacheable accesses |
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82 | * Default cache mode is *disabled* (cache only ACRx areas) |
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83 | */ |
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84 | static uint32_t cacr_mode = MCF5XXX_CACR_CENB | |
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85 | MCF5XXX_CACR_DBWE | |
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86 | MCF5XXX_CACR_DCM; |
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87 | /* |
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88 | * Cannot be frozen |
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89 | */ |
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90 | void _CPU_cache_freeze_data(void) {} |
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91 | void _CPU_cache_unfreeze_data(void) {} |
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92 | void _CPU_cache_freeze_instruction(void) {} |
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93 | void _CPU_cache_unfreeze_instruction(void) {} |
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94 | |
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95 | /* |
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96 | * Write-through data cache -- flushes are unnecessary |
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97 | */ |
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98 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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99 | void _CPU_cache_flush_entire_data(void) {} |
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100 | |
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101 | void _CPU_cache_enable_instruction(void) |
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102 | { |
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103 | rtems_interrupt_level level; |
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104 | |
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105 | rtems_interrupt_disable(level); |
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106 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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107 | m68k_set_cacr(cacr_mode); |
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108 | rtems_interrupt_enable(level); |
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109 | } |
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110 | |
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111 | void _CPU_cache_disable_instruction(void) |
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112 | { |
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113 | rtems_interrupt_level level; |
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114 | |
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115 | rtems_interrupt_disable(level); |
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116 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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117 | m68k_set_cacr(cacr_mode); |
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118 | rtems_interrupt_enable(level); |
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119 | } |
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120 | |
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121 | void _CPU_cache_invalidate_entire_instruction(void) |
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122 | { |
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123 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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124 | } |
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125 | |
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126 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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127 | { |
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128 | /* |
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129 | * Top half of cache is I-space |
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130 | */ |
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131 | addr = (void *)((int)addr | 0x400); |
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132 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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133 | } |
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134 | |
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135 | void _CPU_cache_enable_data(void) |
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136 | { |
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137 | rtems_interrupt_level level; |
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138 | |
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139 | rtems_interrupt_disable(level); |
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140 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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141 | m68k_set_cacr(cacr_mode); |
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142 | rtems_interrupt_enable(level); |
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143 | } |
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144 | |
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145 | void _CPU_cache_disable_data(void) |
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146 | { |
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147 | rtems_interrupt_level level; |
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148 | |
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149 | rtems_interrupt_disable(level); |
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150 | rtems_interrupt_disable(level); |
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151 | cacr_mode |= MCF5XXX_CACR_DISD; |
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152 | m68k_set_cacr(cacr_mode); |
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153 | rtems_interrupt_enable(level); |
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154 | } |
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155 | |
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156 | void _CPU_cache_invalidate_entire_data(void) |
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157 | { |
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158 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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159 | } |
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160 | |
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161 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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162 | { |
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163 | /* |
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164 | * Bottom half of cache is D-space |
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165 | */ |
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166 | addr = (void *)((int)addr & ~0x400); |
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167 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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168 | } |
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169 | |
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170 | /* |
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171 | * Use the shared implementations of the following routines |
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172 | */ |
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173 | void bsp_postdriver_hook(void); |
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174 | void bsp_libc_init( void *, uint32_t, int ); |
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175 | void bsp_pretasking_hook(void); /* m68k version */ |
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176 | |
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177 | /* |
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178 | * bsp_start |
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179 | * |
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180 | * This routine does the bulk of the system initialisation. |
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181 | */ |
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182 | void bsp_start( void ) |
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183 | { |
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184 | extern char _WorkspaceBase[]; |
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185 | extern char _RamBase[], _RamSize[]; |
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186 | extern unsigned long _M68k_Ramsize; |
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187 | |
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188 | _M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */ |
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189 | |
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190 | /* |
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191 | * Allocate the memory for the RTEMS Work Space. This can come from |
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192 | * a variety of places: hard coded address, malloc'ed from outside |
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193 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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194 | * typically done by stock BSPs) by subtracting the required amount |
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195 | * of work space from the last physical address on the CPU board. |
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196 | */ |
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197 | |
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198 | /* |
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199 | * Need to "allocate" the memory for the RTEMS Workspace and |
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200 | * tell the RTEMS configuration where it is. This memory is |
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201 | * not malloc'ed. It is just "pulled from the air". |
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202 | */ |
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203 | |
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204 | BSP_Configuration.work_space_start = (void *)_WorkspaceBase; |
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205 | |
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206 | /* |
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207 | * initialize the CPU table for this BSP |
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208 | */ |
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209 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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210 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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211 | Cpu_table.do_zero_of_workspace = TRUE; |
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212 | Cpu_table.interrupt_stack_size = 4096; |
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213 | |
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214 | Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */ |
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215 | |
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216 | /* |
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217 | * Invalidate the cache and disable it |
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218 | */ |
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219 | m68k_set_acr0(0); |
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220 | m68k_set_acr1(0); |
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221 | m68k_set_cacr(MCF5XXX_CACR_CINV); |
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222 | |
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223 | /* |
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224 | * Cache SDRAM |
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225 | */ |
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226 | m68k_set_acr0(MCF5XXX_ACR_AB((uint32_t)_RamBase) | |
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227 | MCF5XXX_ACR_AM((uint32_t)_RamSize-1) | |
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228 | MCF5XXX_ACR_EN | |
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229 | MCF5XXX_ACR_BWE | |
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230 | MCF5XXX_ACR_SM_IGNORE); |
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231 | |
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232 | /* |
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233 | * Enable the cache |
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234 | */ |
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235 | m68k_set_cacr(cacr_mode); |
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236 | |
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237 | /* |
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238 | * Set up CS* space (fake 'VME') |
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239 | * Two A24/D16 spaces, supervisor data acces |
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240 | */ |
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241 | MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE); |
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242 | MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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243 | MCF5282_CS_CSMR_CI | |
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244 | MCF5282_CS_CSMR_SC | |
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245 | MCF5282_CS_CSMR_UC | |
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246 | MCF5282_CS_CSMR_UD | |
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247 | MCF5282_CS_CSMR_V; |
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248 | MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16; |
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249 | MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE); |
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250 | MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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251 | MCF5282_CS_CSMR_CI | |
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252 | MCF5282_CS_CSMR_SC | |
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253 | MCF5282_CS_CSMR_UC | |
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254 | MCF5282_CS_CSMR_UD | |
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255 | MCF5282_CS_CSMR_V; |
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256 | MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16; |
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257 | } |
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258 | |
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259 | uint32_t bsp_get_CPU_clock_speed(void) |
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260 | { |
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261 | extern char _CPUClockSpeed[]; |
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262 | return( (uint32_t)_CPUClockSpeed); |
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263 | } |
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264 | |
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265 | /* |
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266 | * Interrupt controller allocation |
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267 | */ |
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268 | rtems_status_code |
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269 | bsp_allocate_interrupt(int level, int priority) |
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270 | { |
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271 | static char used[7]; |
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272 | rtems_interrupt_level l; |
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273 | rtems_status_code ret = RTEMS_RESOURCE_IN_USE; |
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274 | |
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275 | if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) |
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276 | return RTEMS_INVALID_NUMBER; |
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277 | rtems_interrupt_disable(l); |
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278 | if ((used[level-1] & (1 << priority)) == 0) { |
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279 | used[level-1] |= (1 << priority); |
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280 | ret = RTEMS_SUCCESSFUL; |
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281 | } |
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282 | rtems_interrupt_enable(l); |
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283 | return ret; |
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284 | } |
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285 | |
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286 | /* |
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287 | * Arcturus bootloader system calls |
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288 | */ |
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289 | #define syscall_return(type, ret) \ |
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290 | do { \ |
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291 | if ((unsigned long)(ret) >= (unsigned long)(-64)) { \ |
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292 | errno = -(ret); \ |
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293 | ret = -1; \ |
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294 | } \ |
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295 | return (type)(ret); \ |
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296 | } while (0) |
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297 | #define syscall_1(type,name,d1type,d1) \ |
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298 | type bsp_##name(d1type d1) \ |
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299 | { \ |
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300 | long ret; \ |
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301 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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302 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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303 | "trap #2\n\t" \ |
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304 | "move.l %%d0,%0" \ |
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305 | : "=g" (ret) \ |
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306 | : "i" (SysCode_##name), "d" (__d1) \ |
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307 | : "d0" ); \ |
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308 | syscall_return(type,ret); \ |
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309 | } |
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310 | #define syscall_2(type,name,d1type,d1,d2type,d2) \ |
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311 | type bsp_##name(d1type d1, d2type d2) \ |
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312 | { \ |
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313 | long ret; \ |
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314 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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315 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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316 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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317 | "trap #2\n\t" \ |
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318 | "move.l %%d0,%0" \ |
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319 | : "=g" (ret) \ |
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320 | : "i" (SysCode_##name), "d" (__d1),\ |
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321 | "d" (__d2) \ |
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322 | : "d0" ); \ |
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323 | syscall_return(type,ret); \ |
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324 | } |
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325 | #define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \ |
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326 | type bsp_##name(d1type d1, d2type d2, d3type d3) \ |
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327 | { \ |
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328 | long ret; \ |
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329 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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330 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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331 | register long __d3 __asm__ ("%d3") = (long)d3; \ |
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332 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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333 | "trap #2\n\t" \ |
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334 | "move.l %%d0,%0" \ |
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335 | : "=g" (ret) \ |
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336 | : "i" (SysCode_##name), "d" (__d1),\ |
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337 | "d" (__d2),\ |
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338 | "d" (__d3) \ |
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339 | : "d0" ); \ |
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340 | syscall_return(type,ret); \ |
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341 | } |
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342 | #define SysCode_reset 0 /* reset */ |
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343 | #define SysCode_program 5 /* program flash memory */ |
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344 | #define SysCode_gethwaddr 12 /* get hardware address */ |
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345 | #define SysCode_getbenv 14 /* get bootloader environment variable */ |
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346 | #define SysCode_setbenv 15 /* get bootloader environment variable */ |
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347 | #define SysCode_flash_erase_range 19 /* erase a section of flash */ |
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348 | #define SysCode_flash_write_range 20 /* write a section of flash */ |
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349 | syscall_1(unsigned const char *, gethwaddr, int, a) |
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350 | syscall_1(const char *, getbenv, const char *, a) |
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351 | syscall_2(int, program, bsp_mnode_t *, chain, int, flags) |
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352 | syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end); |
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353 | syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset); |
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354 | |
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355 | /* |
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356 | * 'Extended BSP' routines |
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357 | * Should move to cpukit/score/cpu/m68k/cpu.c someday. |
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358 | */ |
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359 | |
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360 | rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; } |
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361 | int BSP_enableVME_int_lvl(unsigned int level) { return 0; } |
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362 | int BSP_disableVME_int_lvl(unsigned int level) { return 0; } |
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363 | |
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364 | /* |
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365 | * 'VME' interrupt support |
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366 | * Interrupt vectors 192-255 are set aside for use by external logic which |
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367 | * drives IRQ1*. The actual interrupt source is read from the external |
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368 | * logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant |
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369 | * byte read from this location is set as long as the external logic has |
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370 | * interrupts to be serviced. The least-significant six bits indicate the |
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371 | * interrupt source within the external logic and are used to select the |
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372 | * specified interupt handler. |
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373 | */ |
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374 | #define NVECTOR 256 |
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375 | #define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */ |
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376 | #define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_LEVEL |
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377 | #define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1 |
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378 | #define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1 |
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379 | #define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1 |
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380 | #define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe)) |
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381 | |
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382 | static struct handlerTab { |
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383 | BSP_VME_ISR_t func; |
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384 | void *arg; |
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385 | } handlerTab[NVECTOR]; |
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386 | |
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387 | BSP_VME_ISR_t |
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388 | BSP_getVME_isr(unsigned long vector, void **pusrArg) |
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389 | { |
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390 | if (vector >= NVECTOR) |
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391 | return (BSP_VME_ISR_t)NULL; |
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392 | if (pusrArg) |
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393 | *pusrArg = handlerTab[vector].arg; |
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394 | return handlerTab[vector].func; |
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395 | } |
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396 | |
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397 | static rtems_isr |
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398 | trampoline (rtems_vector_number v) |
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399 | { |
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400 | /* |
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401 | * Handle FPGA interrupts until all have been consumed |
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402 | */ |
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403 | if (v == FPGA_VECTOR) { |
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404 | while (((v = FPGA_IRQ_INFO) & 0x80) != 0) { |
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405 | v = 192 + (v & 0x3f); |
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406 | if (handlerTab[v].func) |
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407 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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408 | else |
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409 | rtems_fatal_error_occurred(v); |
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410 | } |
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411 | } |
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412 | else if (handlerTab[v].func) |
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413 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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414 | } |
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415 | |
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416 | int |
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417 | BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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418 | { |
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419 | rtems_isr_entry old_handler; |
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420 | rtems_interrupt_level level; |
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421 | |
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422 | /* |
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423 | * Register the handler information |
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424 | */ |
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425 | if (vector >= NVECTOR) |
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426 | return -1; |
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427 | handlerTab[vector].func = handler; |
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428 | handlerTab[vector].arg = usrArg; |
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429 | |
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430 | /* |
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431 | * If this is an external FPGA ('VME') vector set up the real IRQ. |
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432 | */ |
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433 | if ((vector >= 192) && (vector <= 255)) { |
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434 | int i; |
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435 | static volatile int setupDone; |
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436 | rtems_interrupt_disable(level); |
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437 | if (setupDone) { |
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438 | rtems_interrupt_enable(level); |
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439 | return 0; |
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440 | } |
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441 | MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR; |
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442 | MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR; |
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443 | MCF5282_EPORT_EPIER |= FPGA_EPIER; |
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444 | MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 | |
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445 | MCF5282_INTC_IMRL_MASKALL); |
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446 | setupDone = 1; |
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447 | i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL); |
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448 | rtems_interrupt_enable(level); |
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449 | return i; |
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450 | } |
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451 | |
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452 | /* |
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453 | * Make the connection between the interrupt and the local handler |
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454 | */ |
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455 | rtems_interrupt_catch(trampoline, vector, &old_handler); |
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456 | |
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457 | /* |
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458 | * Find an unused level/priority if this is an on-chip (INTC0) |
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459 | * source and this is the first time the source is being used. |
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460 | * Interrupt sources 1 through 7 are fixed level/priority |
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461 | */ |
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462 | if ((vector >= 65) && (vector <= 127)) { |
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463 | int l, p; |
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464 | int source = vector - 64; |
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465 | static unsigned char installed[8]; |
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466 | |
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467 | rtems_interrupt_disable(level); |
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468 | if (installed[source/8] & (1 << (source % 8))) { |
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469 | rtems_interrupt_enable(level); |
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470 | return 0; |
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471 | } |
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472 | installed[source/8] |= (1 << (source % 8)); |
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473 | rtems_interrupt_enable(level); |
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474 | for (l = 1 ; l < 7 ; l++) { |
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475 | for (p = 0 ; p < 8 ; p++) { |
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476 | if ((source < 8) |
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477 | || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) { |
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478 | if (source >= 8) |
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479 | *(&MCF5282_INTC0_ICR1 + (source - 1)) = |
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480 | MCF5282_INTC_ICR_IL(l) | |
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481 | MCF5282_INTC_ICR_IP(p); |
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482 | rtems_interrupt_disable(level); |
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483 | if (source >= 32) |
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484 | MCF5282_INTC0_IMRH &= ~(1 << (source - 32)); |
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485 | else |
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486 | MCF5282_INTC0_IMRL &= ~((1 << source) | |
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487 | MCF5282_INTC_IMRL_MASKALL); |
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488 | rtems_interrupt_enable(level); |
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489 | return 0; |
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490 | } |
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491 | } |
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492 | } |
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493 | return -1; |
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494 | } |
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495 | return 0; |
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496 | } |
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497 | |
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498 | int |
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499 | BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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500 | { |
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501 | if (vector >= NVECTOR) |
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502 | return -1; |
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503 | if ((handlerTab[vector].func != handler) |
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504 | || (handlerTab[vector].arg != usrArg)) |
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505 | return -1; |
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506 | handlerTab[vector].func = (BSP_VME_ISR_t)NULL; |
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507 | return 0; |
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508 | } |
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509 | |
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510 | int |
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511 | BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr) |
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512 | { |
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513 | unsigned long offset; |
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514 | |
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515 | switch (am) { |
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516 | default: return -1; |
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517 | case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */ |
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518 | case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */ |
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519 | case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */ |
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520 | } |
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521 | *plocaladdr = vmeaddr + offset; |
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522 | return 0; |
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523 | } |
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