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source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 9f9412c

Last change on this file since 9f9412c was 100673c, checked in by Eric Norum <WENorum@…>, on 02/08/07 at 19:10:18
Fixed FPGA interrupt handling.
Property mode set to `100644`
File size: 22.5 KB

Line
1	/*
2	* BSP startup
3	*
4	* This routine starts the application. It includes application,
5	* board, and monitor specific initialization and configuration.
6	* The generic CPU dependent initialization has been performed
7	* before this routine is invoked.
8	*
9	* Author: W. Eric Norum <norume@aps.anl.gov>
10	*
11	* COPYRIGHT (c) 2005.
12	* On-Line Applications Research Corporation (OAR).
13	*
14	* The license and distribution terms for this file may be
15	* found in the file LICENSE in this distribution or at
16	* http://www.OARcorp.com/rtems/license.html.
17	*
18	* $Id$
19	*/
20
21	#include <bsp.h>
22	#include <rtems/libio.h>
23	#include <rtems/error.h>
24	#include <rtems/libcsupport.h>
25	#include <stdio.h>
26	#include <string.h>
27	#include <errno.h>
28
29	/*
30	* The original table from the application and our copy of it with
31	* some changes.
32	*/
33	extern rtems_configuration_table Configuration;
34	rtems_configuration_table BSP_Configuration;
35	rtems_cpu_table Cpu_table;
36	char *rtems_progname;
37
38	/*
39	* Location of 'VME' access
40	*/
41	#define VME_ONE_BASE 0x30000000
42	#define VME_TWO_BASE 0x31000000
43
44	/*
45	* CPU-space access
46	* The NOP after writing the CACR is there to address the following issue as
47	* described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
48	*
49	* 6 Possible Cache Corruption after Setting CACR[CINV]
50	* 6.1 Description
51	* The cache on the MCF5282 was enhanced to function as a unified data and
52	* instruction cache, an instruction cache, or an operand cache. The cache
53	* function and organization is controlled by the cache control register (CACR).
54	* The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
55	* If the cache is configured as a unified cache and the CINV bit is set, the
56	* scope of the cache clear is controlled by two other bits in the CACR,
57	* INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
58	* cache only). These bits allow the entire cache, just the instruction
59	* portion of the cache, or just the data portion of the cache to be cleared.
60	* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
61	* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
62	* then cache corruption may occur.
63	*
64	* 6.2 Workaround
65	* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
66	* should be followed immediately by a NOP instruction. This avoids the cache
67	* corruption problem.
68	* DATECODES AFFECTED: All
69	*/
70	#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
71	#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
72	#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
73	#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
74
75	/*
76	* Read/write copy of cache registers
77	* Split instruction/data or instruction-only
78	* Allow CPUSHL to invalidate a cache line
79	* Enable buffered writes
80	* No burst transfers on non-cacheable accesses
81	* Default cache mode is disabled (cache only ACRx areas)
82	*/
83	uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB \|
84	#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
85	MCF5XXX_CACR_DISD \|
86	#endif
87	MCF5XXX_CACR_DBWE \|
88	MCF5XXX_CACR_DCM;
89	uint32_t mcf5282_acr0_mode = 0;
90	uint32_t mcf5282_acr1_mode = 0;
91	/*
92	* Cannot be frozen
93	*/
94	void _CPU_cache_freeze_data(void) {}
95	void _CPU_cache_unfreeze_data(void) {}
96	void _CPU_cache_freeze_instruction(void) {}
97	void _CPU_cache_unfreeze_instruction(void) {}
98
99	/*
100	* Write-through data cache -- flushes are unnecessary
101	*/
102	void _CPU_cache_flush_1_data_line(const void *d_addr) {}
103	void _CPU_cache_flush_entire_data(void) {}
104
105	void _CPU_cache_enable_instruction(void)
106	{
107	rtems_interrupt_level level;
108
109	rtems_interrupt_disable(level);
110	mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
111	m68k_set_cacr(mcf5282_cacr_mode);
112	rtems_interrupt_enable(level);
113	}
114
115	void _CPU_cache_disable_instruction(void)
116	{
117	rtems_interrupt_level level;
118
119	rtems_interrupt_disable(level);
120	mcf5282_cacr_mode \|= MCF5XXX_CACR_DIDI;
121	m68k_set_cacr(mcf5282_cacr_mode);
122	rtems_interrupt_enable(level);
123	}
124
125	void _CPU_cache_invalidate_entire_instruction(void)
126	{
127	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVI);
128	}
129
130	void _CPU_cache_invalidate_1_instruction_line(const void *addr)
131	{
132	/*
133	* Top half of cache is I-space
134	*/
135	addr = (void *)((int)addr \| 0x400);
136	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
137	}
138
139	void _CPU_cache_enable_data(void)
140	{
141	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
142	rtems_interrupt_level level;
143
144	rtems_interrupt_disable(level);
145	mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
146	m68k_set_cacr(mcf5282_cacr_mode);
147	rtems_interrupt_enable(level);
148	#endif
149	}
150
151	void _CPU_cache_disable_data(void)
152	{
153	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
154	rtems_interrupt_level level;
155
156	rtems_interrupt_disable(level);
157	rtems_interrupt_disable(level);
158	mcf5282_cacr_mode \|= MCF5XXX_CACR_CENB;
159	m68k_set_cacr(mcf5282_cacr_mode);
160	rtems_interrupt_enable(level);
161	#endif
162	}
163
164	void _CPU_cache_invalidate_entire_data(void)
165	{
166	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
167	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVD);
168	#endif
169	}
170
171	void _CPU_cache_invalidate_1_data_line(const void *addr)
172	{
173	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
174	/*
175	* Bottom half of cache is D-space
176	*/
177	addr = (void *)((int)addr & ~0x400);
178	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
179	#endif
180	}
181
182	/*
183	* Use the shared implementations of the following routines
184	*/
185	void bsp_postdriver_hook(void);
186	void bsp_libc_init( void *, uint32_t, int );
187	void bsp_pretasking_hook(void); /* m68k version */
188
189	/*
190	* The Arcturus boot ROM prints exception information improperly
191	* so use this default exception handler instead. This one also
192	* prints a call backtrace
193	*/
194	static void handler(int pc)
195	{
196	int level;
197	static volatile int reent;
198	extern char _RamSize[];
199
200	rtems_interrupt_disable(level);
201	if (reent++) bsp_reset(0);
202	{
203	int *p = &pc;
204	int info = p[-1];
205	int pc = p[0];
206	int format = (info >> 28) & 0xF;
207	int faultStatus = ((info >> 24) & 0xC) \| ((info >> 16) & 0x3);
208	int vector = (info >> 18) & 0xFF;
209	int statusRegister = info & 0xFFFF;
210	int *fp;
211
212	printk("\n\nPC:%x SR:%x VEC:%x FORMAT:%x STATUS:%x\n", pc,
213	statusRegister,
214	vector,
215	format,
216	faultStatus);
217	fp = &p[-2];
218	for(;;) {
219	int nfp = (int )*fp;
220	if ((nfp <= fp)
221	\|\| ((char *)nfp >= _RamSize)
222	\|\| ((char *)(nfp[1]) >= _RamSize))
223	break;
224	printk("FP:%x -> %x PC:%x\n", fp, nfp, nfp[1]);
225	fp = nfp;
226	}
227	}
228	rtems_task_suspend(0);
229	rtems_panic("done");
230	}
231
232	/*
233	* bsp_start
234	*
235	* This routine does the bulk of the system initialisation.
236	*/
237	void bsp_start( void )
238	{
239	int i;
240	extern char _WorkspaceBase[];
241	extern char _RamBase[], _RamSize[];
242	extern unsigned long _M68k_Ramsize;
243
244	_M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */
245
246	/*
247	* Allocate the memory for the RTEMS Work Space. This can come from
248	* a variety of places: hard coded address, malloc'ed from outside
249	* RTEMS world (e.g. simulator or primitive memory manager), or (as
250	* typically done by stock BSPs) by subtracting the required amount
251	* of work space from the last physical address on the CPU board.
252	*/
253
254	/*
255	* Set up default exception handler
256	*/
257	for (i = 2 ; i < 256 ; i++)
258	if (i != (32+2)) /* Catch all but bootrom system calls */
259	((void ()(int))(i 4)) = handler;
260
261	/*
262	* Need to "allocate" the memory for the RTEMS Workspace and
263	* tell the RTEMS configuration where it is. This memory is
264	* not malloc'ed. It is just "pulled from the air".
265	*/
266
267	BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
268
269	/*
270	* initialize the CPU table for this BSP
271	*/
272	Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
273	Cpu_table.postdriver_hook = bsp_postdriver_hook;
274	Cpu_table.do_zero_of_workspace = TRUE;
275	Cpu_table.interrupt_stack_size = 4096;
276	{
277	extern void _BSP_Thread_Idle_body(void);
278	Cpu_table.idle_task = _BSP_Thread_Idle_body;
279	}
280	Cpu_table.interrupt_vector_table = (m68k_isr )0; / vectors at start of RAM */
281
282	/*
283	* Invalidate the cache and disable it
284	*/
285	m68k_set_acr0(mcf5282_acr0_mode);
286	m68k_set_acr1(mcf5282_acr1_mode);
287	m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
288
289	/*
290	* Cache SDRAM
291	*/
292	mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase) \|
293	MCF5XXX_ACR_AM((uint32_t)_RamSize-1) \|
294	MCF5XXX_ACR_EN \|
295	MCF5XXX_ACR_BWE \|
296	MCF5XXX_ACR_SM_IGNORE;
297	m68k_set_acr0(mcf5282_acr0_mode);
298
299	/*
300	* Enable the cache
301	*/
302	m68k_set_cacr(mcf5282_cacr_mode);
303
304	/*
305	* Set up CS* space (fake 'VME')
306	* Two A24/D16 spaces, supervisor data acces
307	*/
308	MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
309	MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M \|
310	MCF5282_CS_CSMR_CI \|
311	MCF5282_CS_CSMR_SC \|
312	MCF5282_CS_CSMR_UC \|
313	MCF5282_CS_CSMR_UD \|
314	MCF5282_CS_CSMR_V;
315	MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
316	MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
317	MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M \|
318	MCF5282_CS_CSMR_CI \|
319	MCF5282_CS_CSMR_SC \|
320	MCF5282_CS_CSMR_UC \|
321	MCF5282_CS_CSMR_UD \|
322	MCF5282_CS_CSMR_V;
323	MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
324	MCF5282_GPIO_PJPAR \|= 0x06;
325	}
326
327	uint32_t bsp_get_CPU_clock_speed(void)
328	{
329	extern char _CPUClockSpeed[];
330	return( (uint32_t)_CPUClockSpeed);
331	}
332
333	/*
334	* Interrupt controller allocation
335	*/
336	rtems_status_code
337	bsp_allocate_interrupt(int level, int priority)
338	{
339	static char used[7];
340	rtems_interrupt_level l;
341	rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
342
343	if ((level < 1) \|\| (level > 7) \|\| (priority < 0) \|\| (priority > 7))
344	return RTEMS_INVALID_NUMBER;
345	rtems_interrupt_disable(l);
346	if ((used[level-1] & (1 << priority)) == 0) {
347	used[level-1] \|= (1 << priority);
348	ret = RTEMS_SUCCESSFUL;
349	}
350	rtems_interrupt_enable(l);
351	return ret;
352	}
353
354	/*
355	* Arcturus bootloader system calls
356	*/
357	#define syscall_return(type, ret) \
358	do { \
359	if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
360	errno = -(ret); \
361	ret = -1; \
362	} \
363	return (type)(ret); \
364	} while (0)
365	#define syscall_1(type,name,d1type,d1) \
366	type bsp_##name(d1type d1) \
367	{ \
368	long ret; \
369	register long __d1 __asm__ ("%d1") = (long)d1; \
370	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
371	"trap #2\n\t" \
372	"move.l %%d0,%0" \
373	: "=g" (ret) \
374	: "i" (SysCode_##name), "d" (__d1) \
375	: "d0" ); \
376	syscall_return(type,ret); \
377	}
378	#define syscall_2(type,name,d1type,d1,d2type,d2) \
379	type bsp_##name(d1type d1, d2type d2) \
380	{ \
381	long ret; \
382	register long __d1 __asm__ ("%d1") = (long)d1; \
383	register long __d2 __asm__ ("%d2") = (long)d2; \
384	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
385	"trap #2\n\t" \
386	"move.l %%d0,%0" \
387	: "=g" (ret) \
388	: "i" (SysCode_##name), "d" (__d1),\
389	"d" (__d2) \
390	: "d0" ); \
391	syscall_return(type,ret); \
392	}
393	#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \
394	type bsp_##name(d1type d1, d2type d2, d3type d3) \
395	{ \
396	long ret; \
397	register long __d1 __asm__ ("%d1") = (long)d1; \
398	register long __d2 __asm__ ("%d2") = (long)d2; \
399	register long __d3 __asm__ ("%d3") = (long)d3; \
400	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
401	"trap #2\n\t" \
402	"move.l %%d0,%0" \
403	: "=g" (ret) \
404	: "i" (SysCode_##name), "d" (__d1),\
405	"d" (__d2),\
406	"d" (__d3) \
407	: "d0" ); \
408	syscall_return(type,ret); \
409	}
410	#define SysCode_reset 0 /* reset */
411	#define SysCode_program 5 /* program flash memory */
412	#define SysCode_gethwaddr 12 /* get hardware address */
413	#define SysCode_getbenv 14 /* get bootloader environment variable */
414	#define SysCode_setbenv 15 /* set bootloader environment variable */
415	#define SysCode_flash_erase_range 19 /* erase a section of flash */
416	#define SysCode_flash_write_range 20 /* write a section of flash */
417	syscall_1(int, reset, int, flags)
418	syscall_1(unsigned const char *, gethwaddr, int, a)
419	syscall_1(const char , getbenv, const char , a)
420	syscall_1(int, setbenv, const char *, a)
421	syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
422	syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
423	syscall_3(int, flash_write_range, volatile unsigned short , flashptr, bsp_mnode_t , chain, int, offset);
424
425	/*
426	* 'Extended BSP' routines
427	* Should move to cpukit/score/cpu/m68k/cpu.c someday.
428	*/
429
430	rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
431	int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
432	int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
433
434	/*
435	* 'VME' interrupt support
436	* Interrupt vectors 192-255 are set aside for use by external logic which
437	* drives IRQ1*. The actual interrupt source is read from the external
438	* logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant
439	* byte read from this location is set as long as the external logic has
440	* interrupts to be serviced. The least-significant six bits indicate the
441	* interrupt source within the external logic and are used to select the
442	* specified interupt handler.
443	*/
444	#define NVECTOR 256
445	#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
446	#define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_LEVEL
447	#define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1
448	#define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1
449	#define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1
450	#define FPGA_IRQ_INFO ((vuint16 )(0x31000000 + 0xfffffe))
451
452	static struct handlerTab {
453	BSP_VME_ISR_t func;
454	void *arg;
455	} handlerTab[NVECTOR];
456
457	BSP_VME_ISR_t
458	BSP_getVME_isr(unsigned long vector, void **pusrArg)
459	{
460	if (vector >= NVECTOR)
461	return (BSP_VME_ISR_t)NULL;
462	if (pusrArg)
463	*pusrArg = handlerTab[vector].arg;
464	return handlerTab[vector].func;
465	}
466
467	static rtems_isr
468	fpga_trampoline (rtems_vector_number v)
469	{
470	/*
471	* Handle FPGA interrupts until all have been consumed
472	*/
473	int loopcount = 0;
474	while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
475	v = 192 + (v & 0x3f);
476	if (++loopcount >= 50) {
477	rtems_interrupt_level level;
478	rtems_interrupt_disable(level);
479	printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f);
480	MCF5282_INTC0_IMRL \|= MCF5282_INTC_IMRL_INT1;
481	rtems_interrupt_enable(level);
482	return;
483	}
484	if (handlerTab[v].func) {
485	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
486	}
487	else {
488	rtems_interrupt_level level;
489	rtems_vector_number nv;
490	rtems_interrupt_disable(level);
491	printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f);
492	if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0)
493	&& ((nv & 0x3f) == (v & 0x3f))) {
494	printk("DISABLING ALL FPGA INTERRUPTS.\n");
495	MCF5282_INTC0_IMRL \|= MCF5282_INTC_IMRL_INT1;
496	}
497	rtems_interrupt_enable(level);
498	return;
499	}
500	}
501	}
502
503	static rtems_isr
504	trampoline (rtems_vector_number v)
505	{
506	if (handlerTab[v].func)
507	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
508	}
509
510	static void
511	enable_irq(unsigned source)
512	{
513	rtems_interrupt_level level;
514	rtems_interrupt_disable(level);
515	if (source >= 32)
516	MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
517	else
518	MCF5282_INTC0_IMRL &= ~((1 << source) \|
519	MCF5282_INTC_IMRL_MASKALL);
520	rtems_interrupt_enable(level);
521	}
522
523	static void
524	disable_irq(unsigned source)
525	{
526	rtems_interrupt_level level;
527
528	rtems_interrupt_disable(level);
529	if (source >= 32)
530	MCF5282_INTC0_IMRH \|= (1 << (source - 32));
531	else
532	MCF5282_INTC0_IMRL \|= (1 << source);
533	rtems_interrupt_enable(level);
534	}
535
536	void
537	BSP_enable_irq_at_pic(rtems_vector_number v)
538	{
539	int source = v - 64;
540
541	if ( source > 0 && source < 64 ) {
542	enable_irq(source);
543	}
544	}
545
546	void
547	BSP_disable_irq_at_pic(rtems_vector_number v)
548	{
549	int source = v - 64;
550
551	if ( source > 0 && source < 64 ) {
552	disable_irq(source);
553	}
554	}
555
556	int
557	BSP_irq_is_enabled_at_pic(rtems_vector_number v)
558	{
559	int source = v - 64;
560
561	if ( source > 0 && source < 64 ) {
562	return ! ((source >= 32) ?
563	MCF5282_INTC0_IMRH & (1 << (source - 32)) :
564	MCF5282_INTC0_IMRL & (1 << source));
565	}
566	return -1;
567	}
568
569
570	static int
571	init_intc0_bit(unsigned long vector)
572	{
573	rtems_interrupt_level level;
574
575	/*
576	* Find an unused level/priority if this is an on-chip (INTC0)
577	* source and this is the first time the source is being used.
578	* Interrupt sources 1 through 7 are fixed level/priority
579	*/
580
581	if ((vector >= 65) && (vector <= 127)) {
582	int l, p;
583	int source = vector - 64;
584	static unsigned char installed[8];
585
586	rtems_interrupt_disable(level);
587	if (installed[source/8] & (1 << (source % 8))) {
588	rtems_interrupt_enable(level);
589	return 0;
590	}
591	installed[source/8] \|= (1 << (source % 8));
592	rtems_interrupt_enable(level);
593	for (l = 1 ; l < 7 ; l++) {
594	for (p = 0 ; p < 8 ; p++) {
595	if ((source < 8)
596	\|\| (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
597	if (source >= 8)
598	*(&MCF5282_INTC0_ICR1 + (source - 1)) =
599	MCF5282_INTC_ICR_IL(l) \|
600	MCF5282_INTC_ICR_IP(p);
601	enable_irq(source);
602	return 0;
603	}
604	}
605	}
606	return -1;
607	}
608	return 0;
609	}
610
611	int
612	BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
613	{
614	rtems_isr_entry old_handler;
615	rtems_interrupt_level level;
616
617	/*
618	* Register the handler information
619	*/
620	if (vector >= NVECTOR)
621	return -1;
622	handlerTab[vector].func = handler;
623	handlerTab[vector].arg = usrArg;
624
625	/*
626	* If this is an external FPGA ('VME') vector set up the real IRQ.
627	*/
628	if ((vector >= 192) && (vector <= 255)) {
629	int i;
630	static volatile int setupDone;
631	rtems_interrupt_disable(level);
632	if (setupDone) {
633	rtems_interrupt_enable(level);
634	return 0;
635	}
636	MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
637	MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
638	MCF5282_EPORT_EPIER \|= FPGA_EPIER;
639	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 \|
640	MCF5282_INTC_IMRL_MASKALL);
641	setupDone = 1;
642	rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler);
643	i = init_intc0_bit(FPGA_VECTOR);
644	rtems_interrupt_enable(level);
645	return i;
646	}
647
648	/*
649	* Make the connection between the interrupt and the local handler
650	*/
651	rtems_interrupt_catch(trampoline, vector, &old_handler);
652
653	return init_intc0_bit(vector);
654	}
655
656	int
657	BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
658	{
659	if (vector >= NVECTOR)
660	return -1;
661	if ((handlerTab[vector].func != handler)
662	\|\| (handlerTab[vector].arg != usrArg))
663	return -1;
664	handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
665	return 0;
666	}
667
668	int
669	BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
670	{
671	unsigned long offset;
672
673	switch (am) {
674	default: return -1;
675	case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
676	case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
677	case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
678	}
679	*plocaladdr = vmeaddr + offset;
680	return 0;
681	}
682
683	void
684	rtems_bsp_reset_cause(char *buf, size_t capacity)
685	{
686	int bit, rsr;
687	size_t i;
688	const char *cp;
689
690	if (buf == NULL)
691	return;
692	if (capacity)
693	buf[0] = '\0';
694	rsr = MCF5282_RESET_RSR;
695	for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) {
696	if (rsr & bit) {
697	switch (bit) {
698	case MCF5282_RESET_RSR_LVD: cp = "Low voltage"; break;
699	case MCF5282_RESET_RSR_SOFT: cp = "Software reset"; break;
700	case MCF5282_RESET_RSR_WDR: cp = "Watchdog reset"; break;
701	case MCF5282_RESET_RSR_POR: cp = "Power-on reset"; break;
702	case MCF5282_RESET_RSR_EXT: cp = "External reset"; break;
703	case MCF5282_RESET_RSR_LOC: cp = "Loss of clock"; break;
704	case MCF5282_RESET_RSR_LOL: cp = "Loss of lock"; break;
705	default: cp = "??"; break;
706	}
707	i += snprintf(buf+i, capacity-i, cp);
708	if (i >= capacity)
709	break;
710	rsr &= ~bit;
711	if (rsr == 0)
712	break;
713	i += snprintf(buf+i, capacity-i, ", ");
714	if (i >= capacity)
715	break;
716	}
717	}
718	}

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