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source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 9797991

4.104.114.95

Last change on this file since 9797991 was 9797991, checked in by Eric Norum <WENorum@…>, on 04/08/08 at 03:19:53
startup/bspstart.c: Clean up non-FPGA use of EPORT interrupts. network/network.c: Track half/full-duplex changes from 4.7 branch.
Property mode set to `100644`
File size: 21.3 KB

Line
1	/*
2	* BSP startup
3	*
4	* This routine starts the application. It includes application,
5	* board, and monitor specific initialization and configuration.
6	* The generic CPU dependent initialization has been performed
7	* before this routine is invoked.
8	*
9	* Author: W. Eric Norum <norume@aps.anl.gov>
10	*
11	* COPYRIGHT (c) 2005.
12	* On-Line Applications Research Corporation (OAR).
13	*
14	* The license and distribution terms for this file may be
15	* found in the file LICENSE in this distribution or at
16	* http://www.rtems.com/license/LICENSE.
17	*
18	* $Id$
19	*/
20
21	#include <bsp.h>
22	#include <rtems/libio.h>
23	#include <rtems/error.h>
24	#include <rtems/libcsupport.h>
25	#include <stdio.h>
26	#include <string.h>
27	#include <errno.h>
28
29	/*
30	* Location of 'VME' access
31	*/
32	#define VME_ONE_BASE 0x30000000
33	#define VME_TWO_BASE 0x31000000
34
35	/*
36	* CPU-space access
37	* The NOP after writing the CACR is there to address the following issue as
38	* described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
39	*
40	* 6 Possible Cache Corruption after Setting CACR[CINV]
41	* 6.1 Description
42	* The cache on the MCF5282 was enhanced to function as a unified data and
43	* instruction cache, an instruction cache, or an operand cache. The cache
44	* function and organization is controlled by the cache control register (CACR).
45	* The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
46	* If the cache is configured as a unified cache and the CINV bit is set, the
47	* scope of the cache clear is controlled by two other bits in the CACR,
48	* INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
49	* cache only). These bits allow the entire cache, just the instruction
50	* portion of the cache, or just the data portion of the cache to be cleared.
51	* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
52	* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
53	* then cache corruption may occur.
54	*
55	* 6.2 Workaround
56	* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
57	* should be followed immediately by a NOP instruction. This avoids the cache
58	* corruption problem.
59	* DATECODES AFFECTED: All
60	*/
61	#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
62	#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
63	#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
64	#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
65
66	/*
67	* Read/write copy of cache registers
68	* Split instruction/data or instruction-only
69	* Allow CPUSHL to invalidate a cache line
70	* Enable buffered writes
71	* No burst transfers on non-cacheable accesses
72	* Default cache mode is disabled (cache only ACRx areas)
73	*/
74	uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB \|
75	#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
76	MCF5XXX_CACR_DISD \|
77	#endif
78	MCF5XXX_CACR_DBWE \|
79	MCF5XXX_CACR_DCM;
80	uint32_t mcf5282_acr0_mode = 0;
81	uint32_t mcf5282_acr1_mode = 0;
82	/*
83	* Cannot be frozen
84	*/
85	void _CPU_cache_freeze_data(void) {}
86	void _CPU_cache_unfreeze_data(void) {}
87	void _CPU_cache_freeze_instruction(void) {}
88	void _CPU_cache_unfreeze_instruction(void) {}
89
90	/*
91	* Write-through data cache -- flushes are unnecessary
92	*/
93	void _CPU_cache_flush_1_data_line(const void *d_addr) {}
94	void _CPU_cache_flush_entire_data(void) {}
95
96	void _CPU_cache_enable_instruction(void)
97	{
98	rtems_interrupt_level level;
99
100	rtems_interrupt_disable(level);
101	mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
102	m68k_set_cacr(mcf5282_cacr_mode);
103	rtems_interrupt_enable(level);
104	}
105
106	void _CPU_cache_disable_instruction(void)
107	{
108	rtems_interrupt_level level;
109
110	rtems_interrupt_disable(level);
111	mcf5282_cacr_mode \|= MCF5XXX_CACR_DIDI;
112	m68k_set_cacr(mcf5282_cacr_mode);
113	rtems_interrupt_enable(level);
114	}
115
116	void _CPU_cache_invalidate_entire_instruction(void)
117	{
118	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVI);
119	}
120
121	void _CPU_cache_invalidate_1_instruction_line(const void *addr)
122	{
123	/*
124	* Top half of cache is I-space
125	*/
126	addr = (void *)((int)addr \| 0x400);
127	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
128	}
129
130	void _CPU_cache_enable_data(void)
131	{
132	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
133	rtems_interrupt_level level;
134
135	rtems_interrupt_disable(level);
136	mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
137	m68k_set_cacr(mcf5282_cacr_mode);
138	rtems_interrupt_enable(level);
139	#endif
140	}
141
142	void _CPU_cache_disable_data(void)
143	{
144	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
145	rtems_interrupt_level level;
146
147	rtems_interrupt_disable(level);
148	rtems_interrupt_disable(level);
149	mcf5282_cacr_mode \|= MCF5XXX_CACR_CENB;
150	m68k_set_cacr(mcf5282_cacr_mode);
151	rtems_interrupt_enable(level);
152	#endif
153	}
154
155	void _CPU_cache_invalidate_entire_data(void)
156	{
157	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
158	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVD);
159	#endif
160	}
161
162	void _CPU_cache_invalidate_1_data_line(const void *addr)
163	{
164	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
165	/*
166	* Bottom half of cache is D-space
167	*/
168	addr = (void *)((int)addr & ~0x400);
169	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
170	#endif
171	}
172
173	/*
174	* Use the shared implementations of the following routines
175	*/
176	void bsp_postdriver_hook(void);
177	void bsp_libc_init( void *, uint32_t, int );
178	void bsp_pretasking_hook(void); /* m68k version */
179
180	/*
181	* The Arcturus boot ROM prints exception information improperly
182	* so use this default exception handler instead. This one also
183	* prints a call backtrace
184	*/
185	static void handler(int pc)
186	{
187	int level;
188	static volatile int reent;
189	extern char _RamSize[];
190
191	rtems_interrupt_disable(level);
192	if (reent++) bsp_reset(0);
193	{
194	int *p = &pc;
195	int info = p[-1];
196	int pc = p[0];
197	int format = (info >> 28) & 0xF;
198	int faultStatus = ((info >> 24) & 0xC) \| ((info >> 16) & 0x3);
199	int vector = (info >> 18) & 0xFF;
200	int statusRegister = info & 0xFFFF;
201	int *fp;
202
203	printk("\n\nPC:%x SR:%x VEC:%x FORMAT:%x STATUS:%x\n", pc,
204	statusRegister,
205	vector,
206	format,
207	faultStatus);
208	fp = &p[-2];
209	for(;;) {
210	int nfp = (int )*fp;
211	if ((nfp <= fp)
212	\|\| ((char *)nfp >= _RamSize)
213	\|\| ((char *)(nfp[1]) >= _RamSize))
214	break;
215	printk("FP:%x -> %x PC:%x\n", fp, nfp, nfp[1]);
216	fp = nfp;
217	}
218	}
219	rtems_task_suspend(0);
220	rtems_panic("done");
221	}
222
223	/*
224	* bsp_start
225	*
226	* This routine does the bulk of the system initialisation.
227	*/
228	void bsp_start( void )
229	{
230	int i;
231	extern char _WorkspaceBase[];
232	extern char _RamBase[], _RamSize[];
233	extern unsigned long _M68k_Ramsize;
234
235	_M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */
236
237	/*
238	* Allocate the memory for the RTEMS Work Space. This can come from
239	* a variety of places: hard coded address, malloc'ed from outside
240	* RTEMS world (e.g. simulator or primitive memory manager), or (as
241	* typically done by stock BSPs) by subtracting the required amount
242	* of work space from the last physical address on the CPU board.
243	*/
244
245	/*
246	* Set up default exception handler
247	*/
248	for (i = 2 ; i < 256 ; i++)
249	if (i != (32+2)) /* Catch all but bootrom system calls */
250	((void ()(int))(i 4)) = handler;
251
252	/*
253	* Need to "allocate" the memory for the RTEMS Workspace and
254	* tell the RTEMS configuration where it is. This memory is
255	* not malloc'ed. It is just "pulled from the air".
256	*/
257
258	Configuration.work_space_start = (void *)_WorkspaceBase;
259
260	/*
261	* Invalidate the cache and disable it
262	*/
263	m68k_set_acr0(mcf5282_acr0_mode);
264	m68k_set_acr1(mcf5282_acr1_mode);
265	m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
266
267	/*
268	* Cache SDRAM
269	*/
270	mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase) \|
271	MCF5XXX_ACR_AM((uint32_t)_RamSize-1) \|
272	MCF5XXX_ACR_EN \|
273	MCF5XXX_ACR_BWE \|
274	MCF5XXX_ACR_SM_IGNORE;
275	m68k_set_acr0(mcf5282_acr0_mode);
276
277	/*
278	* Enable the cache
279	*/
280	m68k_set_cacr(mcf5282_cacr_mode);
281
282	/*
283	* Set up CS* space (fake 'VME')
284	* Two A24/D16 spaces, supervisor data acces
285	*/
286	MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
287	MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M \|
288	MCF5282_CS_CSMR_CI \|
289	MCF5282_CS_CSMR_SC \|
290	MCF5282_CS_CSMR_UC \|
291	MCF5282_CS_CSMR_UD \|
292	MCF5282_CS_CSMR_V;
293	MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
294	MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
295	MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M \|
296	MCF5282_CS_CSMR_CI \|
297	MCF5282_CS_CSMR_SC \|
298	MCF5282_CS_CSMR_UC \|
299	MCF5282_CS_CSMR_UD \|
300	MCF5282_CS_CSMR_V;
301	MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
302	MCF5282_GPIO_PJPAR \|= 0x06;
303	}
304
305	uint32_t bsp_get_CPU_clock_speed(void)
306	{
307	extern char _CPUClockSpeed[];
308	return( (uint32_t)_CPUClockSpeed);
309	}
310
311	/*
312	* Interrupt controller allocation
313	*/
314	rtems_status_code
315	bsp_allocate_interrupt(int level, int priority)
316	{
317	static char used[7];
318	rtems_interrupt_level l;
319	rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
320
321	if ((level < 1) \|\| (level > 7) \|\| (priority < 0) \|\| (priority > 7))
322	return RTEMS_INVALID_NUMBER;
323	rtems_interrupt_disable(l);
324	if ((used[level-1] & (1 << priority)) == 0) {
325	used[level-1] \|= (1 << priority);
326	ret = RTEMS_SUCCESSFUL;
327	}
328	rtems_interrupt_enable(l);
329	return ret;
330	}
331
332	/*
333	* Arcturus bootloader system calls
334	*/
335	#define syscall_return(type, ret) \
336	do { \
337	if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
338	errno = -(ret); \
339	ret = -1; \
340	} \
341	return (type)(ret); \
342	} while (0)
343
344	#define syscall_1(type,name,d1type,d1) \
345	type bsp_##name(d1type d1) \
346	{ \
347	long ret; \
348	register long __d1 __asm__ ("%d1") = (long)d1; \
349	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
350	"trap #2\n\t" \
351	"move.l %%d0,%0" \
352	: "=g" (ret) \
353	: "i" (SysCode_##name), "d" (__d1) \
354	: "d0" ); \
355	syscall_return(type,ret); \
356	}
357
358	#define syscall_2(type,name,d1type,d1,d2type,d2) \
359	type bsp_##name(d1type d1, d2type d2) \
360	{ \
361	long ret; \
362	register long __d1 __asm__ ("%d1") = (long)d1; \
363	register long __d2 __asm__ ("%d2") = (long)d2; \
364	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
365	"trap #2\n\t" \
366	"move.l %%d0,%0" \
367	: "=g" (ret) \
368	: "i" (SysCode_##name), "d" (__d1),\
369	"d" (__d2) \
370	: "d0" ); \
371	syscall_return(type,ret); \
372	}
373
374	#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \
375	type bsp_##name(d1type d1, d2type d2, d3type d3) \
376	{ \
377	long ret; \
378	register long __d1 __asm__ ("%d1") = (long)d1; \
379	register long __d2 __asm__ ("%d2") = (long)d2; \
380	register long __d3 __asm__ ("%d3") = (long)d3; \
381	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
382	"trap #2\n\t" \
383	"move.l %%d0,%0" \
384	: "=g" (ret) \
385	: "i" (SysCode_##name), "d" (__d1),\
386	"d" (__d2),\
387	"d" (__d3) \
388	: "d0" ); \
389	syscall_return(type,ret); \
390	}
391
392	#define SysCode_reset 0 /* reset */
393	#define SysCode_program 5 /* program flash memory */
394	#define SysCode_gethwaddr 12 /* get hardware address */
395	#define SysCode_getbenv 14 /* get bootloader environment variable */
396	#define SysCode_setbenv 15 /* set bootloader environment variable */
397	#define SysCode_flash_erase_range 19 /* erase a section of flash */
398	#define SysCode_flash_write_range 20 /* write a section of flash */
399	syscall_1(int, reset, int, flags)
400	syscall_1(unsigned const char *, gethwaddr, int, a)
401	syscall_1(const char , getbenv, const char , a)
402	syscall_1(int, setbenv, const char *, a)
403	syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
404	syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
405	syscall_3(int, flash_write_range, volatile unsigned short , flashptr, bsp_mnode_t , chain, int, offset);
406
407	/*
408	* 'Extended BSP' routines
409	* Should move to cpukit/score/cpu/m68k/cpu.c someday.
410	*/
411
412	rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
413	int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
414	int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
415
416	/*
417	* 'VME' interrupt support
418	* Interrupt vectors 192-255 are set aside for use by external logic which
419	* drives IRQ1*. The actual interrupt source is read from the external
420	* logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant
421	* byte read from this location is set as long as the external logic has
422	* interrupts to be serviced. The least-significant six bits indicate the
423	* interrupt source within the external logic and are used to select the
424	* specified interupt handler.
425	*/
426	#define NVECTOR 256
427	#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
428	#define FPGA_IRQ_INFO ((vuint16 )(0x31000000 + 0xfffffe))
429
430	static struct handlerTab {
431	BSP_VME_ISR_t func;
432	void *arg;
433	} handlerTab[NVECTOR];
434
435	BSP_VME_ISR_t
436	BSP_getVME_isr(unsigned long vector, void **pusrArg)
437	{
438	if (vector >= NVECTOR)
439	return (BSP_VME_ISR_t)NULL;
440	if (pusrArg)
441	*pusrArg = handlerTab[vector].arg;
442	return handlerTab[vector].func;
443	}
444
445	static rtems_isr
446	fpga_trampoline (rtems_vector_number v)
447	{
448	/*
449	* Handle FPGA interrupts until all have been consumed
450	*/
451	int loopcount = 0;
452	while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
453	v = 192 + (v & 0x3f);
454	if (++loopcount >= 50) {
455	rtems_interrupt_level level;
456	rtems_interrupt_disable(level);
457	printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f);
458	MCF5282_INTC0_IMRL \|= MCF5282_INTC_IMRL_INT1;
459	rtems_interrupt_enable(level);
460	return;
461	}
462	if (handlerTab[v].func) {
463	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
464	}
465	else {
466	rtems_interrupt_level level;
467	rtems_vector_number nv;
468	rtems_interrupt_disable(level);
469	printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f);
470	if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0)
471	&& ((nv & 0x3f) == (v & 0x3f))) {
472	printk("DISABLING ALL FPGA INTERRUPTS.\n");
473	MCF5282_INTC0_IMRL \|= MCF5282_INTC_IMRL_INT1;
474	}
475	rtems_interrupt_enable(level);
476	return;
477	}
478	}
479	}
480
481	static rtems_isr
482	trampoline (rtems_vector_number v)
483	{
484	if (handlerTab[v].func)
485	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
486	}
487
488	static void
489	enable_irq(unsigned source)
490	{
491	rtems_interrupt_level level;
492	rtems_interrupt_disable(level);
493	if (source >= 32)
494	MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
495	else
496	MCF5282_INTC0_IMRL &= ~((1 << source) \|
497	MCF5282_INTC_IMRL_MASKALL);
498	rtems_interrupt_enable(level);
499	}
500
501	static void
502	disable_irq(unsigned source)
503	{
504	rtems_interrupt_level level;
505
506	rtems_interrupt_disable(level);
507	if (source >= 32)
508	MCF5282_INTC0_IMRH \|= (1 << (source - 32));
509	else
510	MCF5282_INTC0_IMRL \|= (1 << source);
511	rtems_interrupt_enable(level);
512	}
513
514	void
515	BSP_enable_irq_at_pic(rtems_vector_number v)
516	{
517	int source = v - 64;
518
519	if ( source > 0 && source < 64 ) {
520	enable_irq(source);
521	}
522	}
523
524	void
525	BSP_disable_irq_at_pic(rtems_vector_number v)
526	{
527	int source = v - 64;
528
529	if ( source > 0 && source < 64 ) {
530	disable_irq(source);
531	}
532	}
533
534	int
535	BSP_irq_is_enabled_at_pic(rtems_vector_number v)
536	{
537	int source = v - 64;
538
539	if ( source > 0 && source < 64 ) {
540	return ! ((source >= 32) ?
541	MCF5282_INTC0_IMRH & (1 << (source - 32)) :
542	MCF5282_INTC0_IMRL & (1 << source));
543	}
544	return -1;
545	}
546
547
548	static int
549	init_intc0_bit(unsigned long vector)
550	{
551	rtems_interrupt_level level;
552
553	/*
554	* Find an unused level/priority if this is an on-chip (INTC0)
555	* source and this is the first time the source is being used.
556	* Interrupt sources 1 through 7 are fixed level/priority
557	*/
558
559	if ((vector >= 65) && (vector <= 127)) {
560	int l, p;
561	int source = vector - 64;
562	static unsigned char installed[8];
563
564	rtems_interrupt_disable(level);
565	if (installed[source/8] & (1 << (source % 8))) {
566	rtems_interrupt_enable(level);
567	return 0;
568	}
569	installed[source/8] \|= (1 << (source % 8));
570	rtems_interrupt_enable(level);
571	for (l = 1 ; l < 7 ; l++) {
572	for (p = 0 ; p < 8 ; p++) {
573	if ((source < 8)
574	\|\| (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
575	if (source < 8)
576	MCF5282_EPORT_EPIER \|= 1 << source;
577	else
578	*(&MCF5282_INTC0_ICR1 + (source - 1)) =
579	MCF5282_INTC_ICR_IL(l) \|
580	MCF5282_INTC_ICR_IP(p);
581	enable_irq(source);
582	return 0;
583	}
584	}
585	}
586	return -1;
587	}
588	return 0;
589	}
590
591	int
592	BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
593	{
594	rtems_isr_entry old_handler;
595	rtems_interrupt_level level;
596
597	/*
598	* Register the handler information
599	*/
600	if (vector >= NVECTOR)
601	return -1;
602	handlerTab[vector].func = handler;
603	handlerTab[vector].arg = usrArg;
604
605	/*
606	* If this is an external FPGA ('VME') vector set up the real IRQ.
607	*/
608	if ((vector >= 192) && (vector <= 255)) {
609	int i;
610	static volatile int setupDone;
611	rtems_interrupt_disable(level);
612	if (setupDone) {
613	rtems_interrupt_enable(level);
614	return 0;
615	}
616	handlerTab[vector].func = NULL;
617	handlerTab[vector].arg = NULL;
618	rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler);
619	i = init_intc0_bit(FPGA_VECTOR);
620	rtems_interrupt_enable(level);
621	return i;
622	}
623
624	/*
625	* Make the connection between the interrupt and the local handler
626	*/
627	rtems_interrupt_catch(trampoline, vector, &old_handler);
628
629	return init_intc0_bit(vector);
630	}
631
632	int
633	BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
634	{
635	if (vector >= NVECTOR)
636	return -1;
637	if ((handlerTab[vector].func != handler)
638	\|\| (handlerTab[vector].arg != usrArg))
639	return -1;
640	handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
641	return 0;
642	}
643
644	int
645	BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
646	{
647	unsigned long offset;
648
649	switch (am) {
650	default: return -1;
651	case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
652	case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
653	case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
654	}
655	*plocaladdr = vmeaddr + offset;
656	return 0;
657	}
658
659	void
660	rtems_bsp_reset_cause(char *buf, size_t capacity)
661	{
662	int bit, rsr;
663	size_t i;
664	const char *cp;
665
666	if (buf == NULL)
667	return;
668	if (capacity)
669	buf[0] = '\0';
670	rsr = MCF5282_RESET_RSR;
671	for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) {
672	if (rsr & bit) {
673	switch (bit) {
674	case MCF5282_RESET_RSR_LVD: cp = "Low voltage"; break;
675	case MCF5282_RESET_RSR_SOFT: cp = "Software reset"; break;
676	case MCF5282_RESET_RSR_WDR: cp = "Watchdog reset"; break;
677	case MCF5282_RESET_RSR_POR: cp = "Power-on reset"; break;
678	case MCF5282_RESET_RSR_EXT: cp = "External reset"; break;
679	case MCF5282_RESET_RSR_LOC: cp = "Loss of clock"; break;
680	case MCF5282_RESET_RSR_LOL: cp = "Loss of lock"; break;
681	default: cp = "??"; break;
682	}
683	i += snprintf(buf+i, capacity-i, cp);
684	if (i >= capacity)
685	break;
686	rsr &= ~bit;
687	if (rsr == 0)
688	break;
689	i += snprintf(buf+i, capacity-i, ", ");
690	if (i >= capacity)
691	break;
692	}
693	}
694	}

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