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source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 91cb065

4.104.114.84.95

Last change on this file since 91cb065 was 91cb065, checked in by Eric Norum <WENorum@…>, on 12/19/05 at 21:23:52
Add another 'extended BSP' routine which returns reboot status register information
Property mode set to `100644`
File size: 19.3 KB

Line
1	/*
2	* BSP startup
3	*
4	* This routine starts the application. It includes application,
5	* board, and monitor specific initialization and configuration.
6	* The generic CPU dependent initialization has been performed
7	* before this routine is invoked.
8	*
9	* Author: W. Eric Norum <norume@aps.anl.gov>
10	*
11	* COPYRIGHT (c) 2005.
12	* On-Line Applications Research Corporation (OAR).
13	*
14	* The license and distribution terms for this file may be
15	* found in the file LICENSE in this distribution or at
16	* http://www.OARcorp.com/rtems/license.html.
17	*
18	* $Id$
19	*/
20
21	#include <bsp.h>
22	#include <rtems/libio.h>
23	#include <rtems/libcsupport.h>
24	#include <stdio.h>
25	#include <string.h>
26	#include <errno.h>
27
28	/*
29	* The original table from the application and our copy of it with
30	* some changes.
31	*/
32	extern rtems_configuration_table Configuration;
33	rtems_configuration_table BSP_Configuration;
34	rtems_cpu_table Cpu_table;
35	char *rtems_progname;
36
37	/*
38	* Location of 'VME' access
39	*/
40	#define VME_ONE_BASE 0x30000000
41	#define VME_TWO_BASE 0x31000000
42
43	/*
44	* CPU-space access
45	* The NOP after writing the CACR is there to address the following issue as
46	* described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
47	*
48	* 6 Possible Cache Corruption after Setting CACR[CINV]
49	* 6.1 Description
50	* The cache on the MCF5282 was enhanced to function as a unified data and
51	* instruction cache, an instruction cache, or an operand cache. The cache
52	* function and organization is controlled by the cache control register (CACR).
53	* The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
54	* If the cache is configured as a unified cache and the CINV bit is set, the
55	* scope of the cache clear is controlled by two other bits in the CACR,
56	* INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
57	* cache only). These bits allow the entire cache, just the instruction
58	* portion of the cache, or just the data portion of the cache to be cleared.
59	* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
60	* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
61	* then cache corruption may occur.
62	*
63	* 6.2 Workaround
64	* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
65	* should be followed immediately by a NOP instruction. This avoids the cache
66	* corruption problem.
67	* DATECODES AFFECTED: All
68	*/
69	#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
70	#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
71	#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
72	#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
73
74	/*
75	* Read/write copy of cache registers
76	* Split instruction/data or instruction-only
77	* Allow CPUSHL to invalidate a cache line
78	* Enable buffered writes
79	* No burst transfers on non-cacheable accesses
80	* Default cache mode is disabled (cache only ACRx areas)
81	*/
82	uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB \|
83	#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
84	MCF5XXX_CACR_DISD \|
85	#endif
86	MCF5XXX_CACR_DBWE \|
87	MCF5XXX_CACR_DCM;
88	uint32_t mcf5282_acr0_mode = 0;
89	uint32_t mcf5282_acr1_mode = 0;
90	/*
91	* Cannot be frozen
92	*/
93	void _CPU_cache_freeze_data(void) {}
94	void _CPU_cache_unfreeze_data(void) {}
95	void _CPU_cache_freeze_instruction(void) {}
96	void _CPU_cache_unfreeze_instruction(void) {}
97
98	/*
99	* Write-through data cache -- flushes are unnecessary
100	*/
101	void _CPU_cache_flush_1_data_line(const void *d_addr) {}
102	void _CPU_cache_flush_entire_data(void) {}
103
104	void _CPU_cache_enable_instruction(void)
105	{
106	rtems_interrupt_level level;
107
108	rtems_interrupt_disable(level);
109	mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
110	m68k_set_cacr(mcf5282_cacr_mode);
111	rtems_interrupt_enable(level);
112	}
113
114	void _CPU_cache_disable_instruction(void)
115	{
116	rtems_interrupt_level level;
117
118	rtems_interrupt_disable(level);
119	mcf5282_cacr_mode \|= MCF5XXX_CACR_DIDI;
120	m68k_set_cacr(mcf5282_cacr_mode);
121	rtems_interrupt_enable(level);
122	}
123
124	void _CPU_cache_invalidate_entire_instruction(void)
125	{
126	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVI);
127	}
128
129	void _CPU_cache_invalidate_1_instruction_line(const void *addr)
130	{
131	/*
132	* Top half of cache is I-space
133	*/
134	addr = (void *)((int)addr \| 0x400);
135	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
136	}
137
138	void _CPU_cache_enable_data(void)
139	{
140	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
141	rtems_interrupt_level level;
142
143	rtems_interrupt_disable(level);
144	mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
145	m68k_set_cacr(mcf5282_cacr_mode);
146	rtems_interrupt_enable(level);
147	#endif
148	}
149
150	void _CPU_cache_disable_data(void)
151	{
152	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
153	rtems_interrupt_level level;
154
155	rtems_interrupt_disable(level);
156	rtems_interrupt_disable(level);
157	mcf5282_cacr_mode \|= MCF5XXX_CACR_CENB;
158	m68k_set_cacr(mcf5282_cacr_mode);
159	rtems_interrupt_enable(level);
160	#endif
161	}
162
163	void _CPU_cache_invalidate_entire_data(void)
164	{
165	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
166	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVD);
167	#endif
168	}
169
170	void _CPU_cache_invalidate_1_data_line(const void *addr)
171	{
172	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
173	/*
174	* Bottom half of cache is D-space
175	*/
176	addr = (void *)((int)addr & ~0x400);
177	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
178	#endif
179	}
180
181	/*
182	* Use the shared implementations of the following routines
183	*/
184	void bsp_postdriver_hook(void);
185	void bsp_libc_init( void *, uint32_t, int );
186	void bsp_pretasking_hook(void); /* m68k version */
187
188	/*
189	* bsp_start
190	*
191	* This routine does the bulk of the system initialisation.
192	*/
193	void bsp_start( void )
194	{
195	extern char _WorkspaceBase[];
196	extern char _RamBase[], _RamSize[];
197	extern unsigned long _M68k_Ramsize;
198
199	_M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */
200
201	/*
202	* Allocate the memory for the RTEMS Work Space. This can come from
203	* a variety of places: hard coded address, malloc'ed from outside
204	* RTEMS world (e.g. simulator or primitive memory manager), or (as
205	* typically done by stock BSPs) by subtracting the required amount
206	* of work space from the last physical address on the CPU board.
207	*/
208
209	/*
210	* Need to "allocate" the memory for the RTEMS Workspace and
211	* tell the RTEMS configuration where it is. This memory is
212	* not malloc'ed. It is just "pulled from the air".
213	*/
214
215	BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
216
217	/*
218	* initialize the CPU table for this BSP
219	*/
220	Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
221	Cpu_table.postdriver_hook = bsp_postdriver_hook;
222	Cpu_table.do_zero_of_workspace = TRUE;
223	Cpu_table.interrupt_stack_size = 4096;
224
225	Cpu_table.interrupt_vector_table = (m68k_isr )0; / vectors at start of RAM */
226
227	/*
228	* Invalidate the cache and disable it
229	*/
230	m68k_set_acr0(mcf5282_acr0_mode);
231	m68k_set_acr1(mcf5282_acr1_mode);
232	m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
233
234	/*
235	* Cache SDRAM
236	*/
237	mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase) \|
238	MCF5XXX_ACR_AM((uint32_t)_RamSize-1) \|
239	MCF5XXX_ACR_EN \|
240	MCF5XXX_ACR_BWE \|
241	MCF5XXX_ACR_SM_IGNORE;
242	m68k_set_acr0(mcf5282_acr0_mode);
243
244	/*
245	* Enable the cache
246	*/
247	m68k_set_cacr(mcf5282_cacr_mode);
248
249	/*
250	* Set up CS* space (fake 'VME')
251	* Two A24/D16 spaces, supervisor data acces
252	*/
253	MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
254	MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M \|
255	MCF5282_CS_CSMR_CI \|
256	MCF5282_CS_CSMR_SC \|
257	MCF5282_CS_CSMR_UC \|
258	MCF5282_CS_CSMR_UD \|
259	MCF5282_CS_CSMR_V;
260	MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
261	MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
262	MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M \|
263	MCF5282_CS_CSMR_CI \|
264	MCF5282_CS_CSMR_SC \|
265	MCF5282_CS_CSMR_UC \|
266	MCF5282_CS_CSMR_UD \|
267	MCF5282_CS_CSMR_V;
268	MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
269	MCF5282_GPIO_PJPAR \|= 0x06;
270	}
271
272	uint32_t bsp_get_CPU_clock_speed(void)
273	{
274	extern char _CPUClockSpeed[];
275	return( (uint32_t)_CPUClockSpeed);
276	}
277
278	/*
279	* Interrupt controller allocation
280	*/
281	rtems_status_code
282	bsp_allocate_interrupt(int level, int priority)
283	{
284	static char used[7];
285	rtems_interrupt_level l;
286	rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
287
288	if ((level < 1) \|\| (level > 7) \|\| (priority < 0) \|\| (priority > 7))
289	return RTEMS_INVALID_NUMBER;
290	rtems_interrupt_disable(l);
291	if ((used[level-1] & (1 << priority)) == 0) {
292	used[level-1] \|= (1 << priority);
293	ret = RTEMS_SUCCESSFUL;
294	}
295	rtems_interrupt_enable(l);
296	return ret;
297	}
298
299	/*
300	* Arcturus bootloader system calls
301	*/
302	#define syscall_return(type, ret) \
303	do { \
304	if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
305	errno = -(ret); \
306	ret = -1; \
307	} \
308	return (type)(ret); \
309	} while (0)
310	#define syscall_1(type,name,d1type,d1) \
311	type bsp_##name(d1type d1) \
312	{ \
313	long ret; \
314	register long __d1 __asm__ ("%d1") = (long)d1; \
315	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
316	"trap #2\n\t" \
317	"move.l %%d0,%0" \
318	: "=g" (ret) \
319	: "i" (SysCode_##name), "d" (__d1) \
320	: "d0" ); \
321	syscall_return(type,ret); \
322	}
323	#define syscall_2(type,name,d1type,d1,d2type,d2) \
324	type bsp_##name(d1type d1, d2type d2) \
325	{ \
326	long ret; \
327	register long __d1 __asm__ ("%d1") = (long)d1; \
328	register long __d2 __asm__ ("%d2") = (long)d2; \
329	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
330	"trap #2\n\t" \
331	"move.l %%d0,%0" \
332	: "=g" (ret) \
333	: "i" (SysCode_##name), "d" (__d1),\
334	"d" (__d2) \
335	: "d0" ); \
336	syscall_return(type,ret); \
337	}
338	#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \
339	type bsp_##name(d1type d1, d2type d2, d3type d3) \
340	{ \
341	long ret; \
342	register long __d1 __asm__ ("%d1") = (long)d1; \
343	register long __d2 __asm__ ("%d2") = (long)d2; \
344	register long __d3 __asm__ ("%d3") = (long)d3; \
345	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
346	"trap #2\n\t" \
347	"move.l %%d0,%0" \
348	: "=g" (ret) \
349	: "i" (SysCode_##name), "d" (__d1),\
350	"d" (__d2),\
351	"d" (__d3) \
352	: "d0" ); \
353	syscall_return(type,ret); \
354	}
355	#define SysCode_reset 0 /* reset */
356	#define SysCode_program 5 /* program flash memory */
357	#define SysCode_gethwaddr 12 /* get hardware address */
358	#define SysCode_getbenv 14 /* get bootloader environment variable */
359	#define SysCode_setbenv 15 /* get bootloader environment variable */
360	#define SysCode_flash_erase_range 19 /* erase a section of flash */
361	#define SysCode_flash_write_range 20 /* write a section of flash */
362	syscall_1(int, reset, int, flags)
363	syscall_1(unsigned const char *, gethwaddr, int, a)
364	syscall_1(const char , getbenv, const char , a)
365	syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
366	syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
367	syscall_3(int, flash_write_range, volatile unsigned short , flashptr, bsp_mnode_t , chain, int, offset);
368
369	/*
370	* 'Extended BSP' routines
371	* Should move to cpukit/score/cpu/m68k/cpu.c someday.
372	*/
373
374	rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
375	int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
376	int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
377
378	/*
379	* 'VME' interrupt support
380	* Interrupt vectors 192-255 are set aside for use by external logic which
381	* drives IRQ1*. The actual interrupt source is read from the external
382	* logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant
383	* byte read from this location is set as long as the external logic has
384	* interrupts to be serviced. The least-significant six bits indicate the
385	* interrupt source within the external logic and are used to select the
386	* specified interupt handler.
387	*/
388	#define NVECTOR 256
389	#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
390	#define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_LEVEL
391	#define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1
392	#define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1
393	#define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1
394	#define FPGA_IRQ_INFO ((vuint16 )(0x31000000 + 0xfffffe))
395
396	static struct handlerTab {
397	BSP_VME_ISR_t func;
398	void *arg;
399	} handlerTab[NVECTOR];
400
401	BSP_VME_ISR_t
402	BSP_getVME_isr(unsigned long vector, void **pusrArg)
403	{
404	if (vector >= NVECTOR)
405	return (BSP_VME_ISR_t)NULL;
406	if (pusrArg)
407	*pusrArg = handlerTab[vector].arg;
408	return handlerTab[vector].func;
409	}
410
411	static rtems_isr
412	trampoline (rtems_vector_number v)
413	{
414	/*
415	* Handle FPGA interrupts until all have been consumed
416	*/
417	if (v == FPGA_VECTOR) {
418	while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
419	v = 192 + (v & 0x3f);
420	if (handlerTab[v].func)
421	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
422	else
423	rtems_fatal_error_occurred(v);
424	}
425	}
426	else if (handlerTab[v].func)
427	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
428	}
429
430	int
431	BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
432	{
433	rtems_isr_entry old_handler;
434	rtems_interrupt_level level;
435
436	/*
437	* Register the handler information
438	*/
439	if (vector >= NVECTOR)
440	return -1;
441	handlerTab[vector].func = handler;
442	handlerTab[vector].arg = usrArg;
443
444	/*
445	* If this is an external FPGA ('VME') vector set up the real IRQ.
446	*/
447	if ((vector >= 192) && (vector <= 255)) {
448	int i;
449	static volatile int setupDone;
450	rtems_interrupt_disable(level);
451	if (setupDone) {
452	rtems_interrupt_enable(level);
453	return 0;
454	}
455	MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
456	MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
457	MCF5282_EPORT_EPIER \|= FPGA_EPIER;
458	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 \|
459	MCF5282_INTC_IMRL_MASKALL);
460	setupDone = 1;
461	i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL);
462	rtems_interrupt_enable(level);
463	return i;
464	}
465
466	/*
467	* Make the connection between the interrupt and the local handler
468	*/
469	rtems_interrupt_catch(trampoline, vector, &old_handler);
470
471	/*
472	* Find an unused level/priority if this is an on-chip (INTC0)
473	* source and this is the first time the source is being used.
474	* Interrupt sources 1 through 7 are fixed level/priority
475	*/
476	if ((vector >= 65) && (vector <= 127)) {
477	int l, p;
478	int source = vector - 64;
479	static unsigned char installed[8];
480
481	rtems_interrupt_disable(level);
482	if (installed[source/8] & (1 << (source % 8))) {
483	rtems_interrupt_enable(level);
484	return 0;
485	}
486	installed[source/8] \|= (1 << (source % 8));
487	rtems_interrupt_enable(level);
488	for (l = 1 ; l < 7 ; l++) {
489	for (p = 0 ; p < 8 ; p++) {
490	if ((source < 8)
491	\|\| (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
492	if (source >= 8)
493	*(&MCF5282_INTC0_ICR1 + (source - 1)) =
494	MCF5282_INTC_ICR_IL(l) \|
495	MCF5282_INTC_ICR_IP(p);
496	rtems_interrupt_disable(level);
497	if (source >= 32)
498	MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
499	else
500	MCF5282_INTC0_IMRL &= ~((1 << source) \|
501	MCF5282_INTC_IMRL_MASKALL);
502	rtems_interrupt_enable(level);
503	return 0;
504	}
505	}
506	}
507	return -1;
508	}
509	return 0;
510	}
511
512	int
513	BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
514	{
515	if (vector >= NVECTOR)
516	return -1;
517	if ((handlerTab[vector].func != handler)
518	\|\| (handlerTab[vector].arg != usrArg))
519	return -1;
520	handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
521	return 0;
522	}
523
524	int
525	BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
526	{
527	unsigned long offset;
528
529	switch (am) {
530	default: return -1;
531	case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
532	case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
533	case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
534	}
535	*plocaladdr = vmeaddr + offset;
536	return 0;
537	}
538
539	void
540	rtems_bsp_reset_cause(char *buf, size_t capacity)
541	{
542	int bit, rsr;
543	size_t i;
544	const char *cp;
545
546	if (buf == NULL)
547	return;
548	if (capacity)
549	buf[0] = '\0';
550	rsr = MCF5282_RESET_RSR;
551	for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) {
552	if (rsr & bit) {
553	switch (bit) {
554	case MCF5282_RESET_RSR_SOFT: cp = "Software reset"; break;
555	case MCF5282_RESET_RSR_WDR: cp = "Watchdog reset"; break;
556	case MCF5282_RESET_RSR_POR: cp = "Power-on reset"; break;
557	case MCF5282_RESET_RSR_EXT: cp = "External reset"; break;
558	case MCF5282_RESET_RSR_LOC: cp = "Loss of clock"; break;
559	case MCF5282_RESET_RSR_LOL: cp = "Loss of lock"; break;
560	default: cp = "??"; break;
561	}
562	i += snprintf(buf+i, capacity-i, cp);
563	if (i >= capacity)
564	break;
565	rsr &= ~bit;
566	if (rsr == 0)
567	break;
568	i += snprintf(buf+i, capacity-i, ", ");
569	if (i >= capacity)
570	break;
571	}
572	}
573	}

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