source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 7eab0f78

4.104.114.84.95
Last change on this file since 7eab0f78 was 7eab0f78, checked in by Eric Norum <WENorum@…>, on Feb 1, 2005 at 5:16:41 PM

Add some bootrom system calls.

  • Property mode set to 100644
File size: 7.9 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
29#include <errno.h>
30 
31/*
32 *  The original table from the application and our copy of it with
33 *  some changes.
34 */
35extern rtems_configuration_table Configuration;
36rtems_configuration_table  BSP_Configuration;
37rtems_cpu_table Cpu_table;
38char *rtems_progname;
39
40/*
41 * Location of 'VME' access
42 */
43#define VME_ONE_BASE    0x30000000
44#define VME_TWO_BASE    0x31000000
45
46/*
47 * Cacheable areas
48 */
49#define SDRAM_BASE      0
50#define SDRAM_SIZE      (16*1024*1024)
51#define FLASH_BASE      0x10C10000
52#define FLASH_SIZE      (4*1024*1024)
53
54/*
55 * CPU-space access
56 */
57#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
58#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
59#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
60
61/*
62 * Read/write copy of common cache
63 *   Split I/D cache
64 *   Allow CPUSHL to invalidate a cache line
65 *   Enable buffered writes
66 *   No burst transfers on non-cacheable accesses
67 *   Default cache mode is *disabled* (cache only ACRx areas)
68 */
69static unsigned32 cacr_mode = MCF5XXX_CACR_CENB |
70                              MCF5XXX_CACR_DBWE |
71                              MCF5XXX_CACR_DCM;
72/*
73 * Cannot be frozen
74 */
75void _CPU_cache_freeze_data(void) {}
76void _CPU_cache_unfreeze_data(void) {}
77void _CPU_cache_freeze_instruction(void) {}
78void _CPU_cache_unfreeze_instruction(void) {}
79
80/*
81 * Write-through data cache -- flushes are unnecessary
82 */
83void _CPU_cache_flush_1_data_line(const void *d_addr) {}
84void _CPU_cache_flush_entire_data(void) {}
85
86void _CPU_cache_enable_instruction(void)
87{
88    rtems_interrupt_level level;
89
90    rtems_interrupt_disable(level);
91    cacr_mode &= ~MCF5XXX_CACR_DIDI;
92    m68k_set_cacr(cacr_mode);
93    rtems_interrupt_enable(level);
94}
95
96void _CPU_cache_disable_instruction(void)
97{
98    rtems_interrupt_level level;
99
100    rtems_interrupt_disable(level);
101    cacr_mode |= MCF5XXX_CACR_DIDI;
102    m68k_set_cacr(cacr_mode);
103    rtems_interrupt_enable(level);
104}
105
106void _CPU_cache_invalidate_entire_instruction(void)
107{
108    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
109}
110
111void _CPU_cache_invalidate_1_instruction_line(const void *addr)
112{
113    /*
114     * Top half of cache is I-space
115     */
116    addr = (void *)((int)addr | 0x400);
117    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
118}
119
120void _CPU_cache_enable_data(void)
121{
122    rtems_interrupt_level level;
123
124    rtems_interrupt_disable(level);
125    cacr_mode &= ~MCF5XXX_CACR_DISD;
126    m68k_set_cacr(cacr_mode);
127    rtems_interrupt_enable(level);
128}
129
130void _CPU_cache_disable_data(void)
131{
132    rtems_interrupt_level level;
133
134    rtems_interrupt_disable(level);
135    rtems_interrupt_disable(level);
136    cacr_mode |= MCF5XXX_CACR_DISD;
137    m68k_set_cacr(cacr_mode);
138    rtems_interrupt_enable(level);
139}
140
141void _CPU_cache_invalidate_entire_data(void)
142{
143    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
144}
145
146void _CPU_cache_invalidate_1_data_line(const void *addr)
147{
148    /*
149     * Bottom half of cache is D-space
150     */
151    addr = (void *)((int)addr & ~0x400);
152    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
153}
154
155/*
156 *  Use the shared implementations of the following routines
157 */
158void bsp_postdriver_hook(void);
159void bsp_libc_init( void *, unsigned32, int );
160void bsp_pretasking_hook(void);                 /* m68k version */
161
162/*
163 *  bsp_start
164 *
165 *  This routine does the bulk of the system initialisation.
166 */
167void bsp_start( void )
168{
169  extern char _WorkspaceBase[];
170  extern char _RamSize[];
171  extern unsigned long  _M68k_Ramsize;
172
173  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
174
175  /*
176   *  Allocate the memory for the RTEMS Work Space.  This can come from
177   *  a variety of places: hard coded address, malloc'ed from outside
178   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
179   *  typically done by stock BSPs) by subtracting the required amount
180   *  of work space from the last physical address on the CPU board.
181   */
182
183  /*
184   *  Need to "allocate" the memory for the RTEMS Workspace and
185   *  tell the RTEMS configuration where it is.  This memory is
186   *  not malloc'ed.  It is just "pulled from the air".
187   */
188
189  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
190
191  /*
192   *  initialize the CPU table for this BSP
193   */
194  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
195  Cpu_table.postdriver_hook = bsp_postdriver_hook;
196  Cpu_table.do_zero_of_workspace = TRUE;
197  Cpu_table.interrupt_stack_size = 4096;
198
199  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
200
201    /*
202     * Invalidate the cache and disable it
203     */
204    m68k_set_acr0(0);
205    m68k_set_acr1(0);
206    m68k_set_cacr(MCF5XXX_CACR_CINV);
207
208    /*
209     * Cache SDRAM and FLASH
210     */
211    m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
212                  MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
213                  MCF5XXX_ACR_EN                |
214                  MCF5XXX_ACR_BWE               |
215                  MCF5XXX_ACR_SM_IGNORE);
216    m68k_set_acr1(MCF5XXX_ACR_AB(FLASH_BASE)    |
217                  MCF5XXX_ACR_AM(FLASH_SIZE-1)  |
218                  MCF5XXX_ACR_EN                |
219                  MCF5XXX_ACR_BWE               |
220                  MCF5XXX_ACR_SM_IGNORE);
221
222    /*
223     * Enable the cache
224     */
225    m68k_set_cacr(cacr_mode);
226
227    /*
228     * Set up CS* space (fake 'VME')
229     *   Two A24/D16 spaces, supervisor data acces
230     */
231    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
232    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | 
233                       MCF5282_CS_CSMR_CI |
234                       MCF5282_CS_CSMR_SC |
235                       MCF5282_CS_CSMR_UC |
236                       MCF5282_CS_CSMR_UD |
237                       MCF5282_CS_CSMR_V;
238    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
239    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
240    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | 
241                       MCF5282_CS_CSMR_CI |
242                       MCF5282_CS_CSMR_SC |
243                       MCF5282_CS_CSMR_UC |
244                       MCF5282_CS_CSMR_UD |
245                       MCF5282_CS_CSMR_V;
246    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
247}
248
249unsigned32 get_CPU_clock_speed(void)
250{
251    extern char _CPUClockSpeed[];
252    return( (unsigned32)_CPUClockSpeed);
253}
254
255/*
256 * Arcturus routines for getting value from bootloader
257 */
258#define __bsc_return(type, res) \
259do { \
260   if ((unsigned long)(res) >= (unsigned long)(-64)) { \
261      errno = -(res); \
262      res = -1; \
263   } \
264   return (type)(res); \
265} while (0)
266#define _bsc1(type,name,atype,a) \
267type uC5282_##name(atype a) \
268{ \
269   long __res; \
270   register long __a __asm__ ("%d1") = (long)a; \
271   __asm__ __volatile__ ("move.l %0,%%d0\n\t"   \
272                         "trap #2\n\t"          \
273                         "move.l %%d0,%0"       \
274                         : "=d" (__res)         \
275                         : "0" (__BN_##name), "d" (__a) \
276                         : "d0" ); \
277   __bsc_return(type,__res); \
278}
279#define __BN_gethwaddr    12 /* get the hardware address of my interfaces */
280#define __BN_getbenv      14 /* get a bootloader envvar */
281#define __BN_setbenv      15 /* get a bootloader envvar */
282_bsc1(unsigned const char *, gethwaddr, int, a)
283_bsc1(char *, getbenv, const char *, a)
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