source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 518edef

4.104.114.84.9
Last change on this file since 518edef was 518edef, checked in by Eric Norum <WENorum@…>, on Jan 31, 2005 at 7:03:41 PM

Processor doesn't snoop FEC DMA so we must invalidate the cache appropriately.

  • Property mode set to 100644
File size: 6.9 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
29 
30/*
31 *  The original table from the application and our copy of it with
32 *  some changes.
33 */
34extern rtems_configuration_table Configuration;
35rtems_configuration_table  BSP_Configuration;
36rtems_cpu_table Cpu_table;
37char *rtems_progname;
38
39/*
40 * Location of 'VME' access
41 */
42#define VME_ONE_BASE    0x30000000
43#define VME_TWO_BASE    0x31000000
44
45/*
46 * Cacheable areas
47 */
48#define SDRAM_BASE      0
49#define SDRAM_SIZE      (16*1024*1024)
50#define FLASH_BASE      0x10C10000
51#define FLASH_SIZE      (4*1024*1024)
52
53/*
54 * CPU-space access
55 */
56#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
57#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
58#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
59
60/*
61 * Read/write copy of common cache
62 *   Split I/D cache
63 *   Allow CPUSHL to invalidate a cache line
64 *   Enable buffered writes
65 *   No burst transfers on non-cacheable accesses
66 *   Default cache mode is *disabled* (cache only ACRx areas)
67 */
68static unsigned32 cacr_mode = MCF5XXX_CACR_CENB |
69                              MCF5XXX_CACR_DBWE |
70                              MCF5XXX_CACR_DCM;
71/*
72 * Cannot be frozen
73 */
74void _CPU_cache_freeze_data(void) {}
75void _CPU_cache_unfreeze_data(void) {}
76void _CPU_cache_freeze_instruction(void) {}
77void _CPU_cache_unfreeze_instruction(void) {}
78
79/*
80 * Write-through data cache -- flushes are unnecessary
81 */
82void _CPU_cache_flush_1_data_line(const void *d_addr) {}
83void _CPU_cache_flush_entire_data(void) {}
84
85void _CPU_cache_enable_instruction(void)
86{
87    rtems_interrupt_level level;
88
89    rtems_interrupt_disable(level);
90    cacr_mode &= ~MCF5XXX_CACR_DIDI;
91    m68k_set_cacr(cacr_mode);
92    rtems_interrupt_enable(level);
93}
94
95void _CPU_cache_disable_instruction(void)
96{
97    rtems_interrupt_level level;
98
99    rtems_interrupt_disable(level);
100    cacr_mode |= MCF5XXX_CACR_DIDI;
101    m68k_set_cacr(cacr_mode);
102    rtems_interrupt_enable(level);
103}
104
105void _CPU_cache_invalidate_entire_instruction(void)
106{
107    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
108}
109
110void _CPU_cache_invalidate_1_instruction_line(const void *addr)
111{
112    /*
113     * Top half of cache is I-space
114     */
115    addr = (void *)((int)addr | 0x400);
116    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
117}
118
119void _CPU_cache_enable_data(void)
120{
121    rtems_interrupt_level level;
122
123    rtems_interrupt_disable(level);
124    cacr_mode &= ~MCF5XXX_CACR_DISD;
125    m68k_set_cacr(cacr_mode);
126    rtems_interrupt_enable(level);
127}
128
129void _CPU_cache_disable_data(void)
130{
131    rtems_interrupt_level level;
132
133    rtems_interrupt_disable(level);
134    rtems_interrupt_disable(level);
135    cacr_mode |= MCF5XXX_CACR_DISD;
136    m68k_set_cacr(cacr_mode);
137    rtems_interrupt_enable(level);
138}
139
140void _CPU_cache_invalidate_entire_data(void)
141{
142    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
143}
144
145void _CPU_cache_invalidate_1_data_line(const void *addr)
146{
147    /*
148     * Bottom half of cache is D-space
149     */
150    addr = (void *)((int)addr & ~0x400);
151    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
152}
153
154/*
155 *  Use the shared implementations of the following routines
156 */
157void bsp_postdriver_hook(void);
158void bsp_libc_init( void *, unsigned32, int );
159void bsp_pretasking_hook(void);                 /* m68k version */
160
161/*
162 *  bsp_start
163 *
164 *  This routine does the bulk of the system initialisation.
165 */
166void bsp_start( void )
167{
168  extern char _WorkspaceBase[];
169  extern char _RamSize[];
170  extern unsigned long  _M68k_Ramsize;
171
172  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
173
174  /*
175   *  Allocate the memory for the RTEMS Work Space.  This can come from
176   *  a variety of places: hard coded address, malloc'ed from outside
177   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
178   *  typically done by stock BSPs) by subtracting the required amount
179   *  of work space from the last physical address on the CPU board.
180   */
181
182  /*
183   *  Need to "allocate" the memory for the RTEMS Workspace and
184   *  tell the RTEMS configuration where it is.  This memory is
185   *  not malloc'ed.  It is just "pulled from the air".
186   */
187
188  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
189
190  /*
191   *  initialize the CPU table for this BSP
192   */
193  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
194  Cpu_table.postdriver_hook = bsp_postdriver_hook;
195  Cpu_table.do_zero_of_workspace = TRUE;
196  Cpu_table.interrupt_stack_size = 4096;
197
198  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
199
200    /*
201     * Invalidate the cache and disable it
202     */
203    m68k_set_acr0(0);
204    m68k_set_acr1(0);
205    m68k_set_cacr(MCF5XXX_CACR_CINV);
206
207    /*
208     * Cache SDRAM and FLASH
209     */
210    m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
211                  MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
212                  MCF5XXX_ACR_EN                |
213                  MCF5XXX_ACR_BWE               |
214                  MCF5XXX_ACR_SM_IGNORE);
215    m68k_set_acr1(MCF5XXX_ACR_AB(FLASH_BASE)    |
216                  MCF5XXX_ACR_AM(FLASH_SIZE-1)  |
217                  MCF5XXX_ACR_EN                |
218                  MCF5XXX_ACR_BWE               |
219                  MCF5XXX_ACR_SM_IGNORE);
220
221    /*
222     * Enable the cache
223     */
224    m68k_set_cacr(cacr_mode);
225
226    /*
227     * Set up CS* space (fake 'VME')
228     *   Two A24/D16 spaces, supervisor data acces
229     */
230    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
231    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | 
232                       MCF5282_CS_CSMR_CI |
233                       MCF5282_CS_CSMR_SC |
234                       MCF5282_CS_CSMR_UC |
235                       MCF5282_CS_CSMR_UD |
236                       MCF5282_CS_CSMR_V;
237    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
238    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
239    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | 
240                       MCF5282_CS_CSMR_CI |
241                       MCF5282_CS_CSMR_SC |
242                       MCF5282_CS_CSMR_UC |
243                       MCF5282_CS_CSMR_UD |
244                       MCF5282_CS_CSMR_V;
245    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
246}
247
248unsigned32 get_CPU_clock_speed(void)
249{
250    extern char _CPUClockSpeed[];
251    return( (unsigned32)_CPUClockSpeed);
252}
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